By Pieter Burggraaf
WaferNews technical editor
Belgium’s independent R&D center IMEC has begun research to develop technology that will give the industry integrated wafer-level packaging on copper low-k IC interconnect, to be done in wafer processing’s back end of the line (BEOL).
It is the view of IMEC technologists that such novel approaches are fundamental for leading-edge CMOS technologies, including IMEC’s work to benchmark and leverage CMOS and BiCMOS for RF applications, which will enable products operating well into the 5 to 25 GHz microwave radio frequencies.
Brief details on the new program were given by Karen Maex, IMEC’s strategic research coordinator for interconnect technologies and silicides, at the center’s annual research review meeting held October 16 to 18 in Leuven, Belgium. Maex said, “We have designed this program to help establish the future functionality of the package as a provider of global interconnects with the chip.”
To address weakness and corrosion susceptibilities of low-k dielectrics, the program first will determine an improved chip passivation to cover Cu low-k interconnect structures.
“With copper interconnect pads there are also issues with oxidation, wire conductability, and interconnect reliability,” said Maex. “So, we are also looking at optimizing bond pad design and direct copper wire bonding onto copper bond pads. For the latter, several tests have already proven feasibility, but more work is needed before this technology reaches the productivity of current state of the art fine pitch gold wire bond equipment.”
The new IMEC program has also targeted solutions to I/O density problems using an I/O bond pad redistribution layer added, at the wafer level, on top of copper low-k integration.
“Using one additional metal layer, we will redistribute perimeter contact pads into an area array. Then, on these contact pads, we will study solder bumping for flip chip connections,” Maex explained. “Here, given environmental requirements to eliminated lead from electronics, we will be focusing on small pitch lead-free bumping.”
She continued, “One very significant advantage of this redistribution technique is that the additional metal layer can be used for high-speed interconnect lines across a die, clock redistribution lines, and even to realize high-Q inductors on chip.”
Because interconnect delay will seriously limit performance as the industry scales to smaller nodes, one of the long-term strategies of the new IMEC program is to develop solutions for minimizing overall on- and off-chip signal delay. Maex said, “Introduction of copper and low-k has only incrementally improved the propagation velocity situation with ICs. We see that the integration of packaging with BEOL processes will allow for new interconnecton concepts that can solve signal-delay problems.”