By Debra Vogler
WaferNews Technical Editor
Traditional yield enhancement techniques focus on analyzing the causes of killer defects – those due to sources of contamination on the wafer and in the factory. However, feature-limited yield is becoming a dominant driver of overall yield as the industry goes further and further into the deep sub-micron (DSM) region.
PDF Solutions specializes in attacking the root causes of systematic yield loss using statistical methods, such as design of experiments (DOE), and comprehensive test chips and analysis software to simulate the interactions between process steps and discover the root causes of loss.
Because the available time for finding and eliminating feature-limited yield problems is dramatically decreasing along with an associated decrease in time-to-volume, finding solutions translates into cash. PDF Solutions refers those interested in this dilemma to the results of a yield learning rate study conducted by U.C. Berkeley. Data suggest that IC manufacturers that are in the top 5% of the defect density learning rate get $200 million yearly applied directly to their bottom line for every 10,000 wafer starts/month.
“There will no longer be enough time during the production ramp to find and fix yield problems,” stated David Joseph, VP of business development at PDF Solutions. “What’s more, if the increasing costs of mask sets are considered – ranging from about $250,000 at the 0.18-micron node to roughly $700,000 for the 0.13-micron node, there is an even greater incentive to avoid making mistakes. The test masks developed by PDF Solutions are designed to be diagnosable at the process module level and that speeds the rate of yield improvement.”
“The majority of yield losses can be isolated to four major ‘modules’,” noted Joseph. “Those four are metallization, vias, contacts, and poly and each can be fully optimized in a manner that is primarily independent from the other. This reduces complexity and improves cycle time. The data needed to drive yield enhancement comes from specific test structures for each of these modules that emulate the environmental variations and frequency of use in actual product designs that are targeted for that process.”
On one particular complex SoC product line with a major IDM, PDF Solutions has customer learning data showing that cost savings from an accelerated time-to-volume and yield enhancement program were greater than $100 million. It was also reported that the product was introduced with a 20% better yield than the previous baseline and a mature yield that was 5% higher than the previous benchmark.