ITRS accelerates pace to smaller chip dimensions

Nov. 29, 2001 – San Jose, CA – The 2001 edition of the International Technology Roadmap for Semiconductors (ITRS) calls for more aggressive scaling than previously planned.

Today’s state-of-the-art semiconductor chips feature technology nodes of 0.18-micron, with 0.13-micron technologies just beginning to reach the marketplace.

In the previous roadmap released in 1999, it called for the future generations of DRAM to feature critical dimensions of 100 nanometers in 2005, then 70 nanometers in 2008, 50 nanometers in 2011 and 35 nanometers in 2014. Now the industry plans to deliver 90 nanometers (2004), 65 nanometers (2007), 45 nanometers (2010), 32 nanometers (2013) and 22 nanometers (2016). This 2001 schedule translates to smaller chip dimensions earlier in time than previously thought.

“Lithography half-pitch and transistor gate length scaling trends continue to accelerate. This means that semiconductor chips will continue to get smaller, faster and ultimately less expensive at an even faster rate in the future,” noted Paolo Gargini, chairman of the International Roadmap committee and fellow, Intel Corp. “When the 2001 Roadmap looks 15 years into the future, the physical gate length is projected to be a mere 9 nanometers. We are beginning to consider technologies beyond planar or even post-CMOS devices.”

“The 2001 edition of the International Technology Roadmap for Semiconductors is the result of worldwide consensus building among 800 experts from the US, Europe, Japan, Korea, and Taiwan. It is a valid source of guidance for the semiconductor industry as we strive to extend the historical advancement of semiconductor technology and the worldwide integrated circuit market,” said Robert Doering, vice-chairman of the International Technology Roadmap for Semiconductors for US Region and senior fellow, Texas Instruments.

The scaling of the smallest feature size in integrated circuits — microprocessor transistor gate lengths — shows just six years until it hits some fundamental limits. At the horizon of the 2001 ITRS (now 2016), the physical gate length is projected to be a mere nine nanometers. This is essentially equivalent to the most optimistic current projections on the extendibility of MOS transistors as well as the smallest experimental MOSFETS ever built. These experimental devices used a special source/drain structure that has not been demonstrated to be practical for high-performance circuits yet.


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