Providing high density and performance for chip-to-system interconnection
BY GARY SOLOMON
Wafer-level chip scale packaging (WL-CSP) delivers true chip size packages by extending integrated circuit wafer processing technology through the packaging process sequence. While these packages currently represent a small fraction of the packaging spectrum, the driving forces of scaling, economy and performance are fueling advances in board, substrate, materials, processing and testing technologies that will enable a more widespread use of WL-CSP.
This article addresses the main process integration topics for electro-chemically deposited (ECD) solder bumps. The majority of the process steps are leveraged from mainstream integrated circuit (IC) manufacturing technology. Adapting these highly developed and characterized process-es to wafer-level packaging has accel-erated the move into production by simplifying the overall integration of the packaging flow.
Wafer-level Packaging Overview
A typical IC process finishes with peripheral bonding pads and moves on to electrical parametric and early functional testing. A wafer-level packaging (WLP) process adds one more level of wiring interconnect to redistribute these pads to an array of solder bump landing pads arranged above the area of the chip circuitry (Figure 1).
 Figure 1. Cross section of redistribution structures from peripheral bond pads to array landing pads. |
Figure 2 shows the process steps from under-bump metallurgy (UBM) through solder reflow for two plating approaches (mushroom plating and within-via plating). The UBM is sput-tered on the entire wafer surface. This metal stack provides adhesion between the landing pad and the upper metal layers, a diffusion barrier between the landing pad and the upper metals, a wettable surface for the solder bump and a conductive seed layer for the elec-troplating process. A thick photoresist via pattern is then defined; this serves as the plating mask. The solder is elec-trochemically deposited, the photore-sist is stripped, and the UBM is etched away between the solder bumps. Flux is also applied and the solder is reflowed. The solder wets only the UBM remain-ing under the bump, and surface ten-sion draws it into the shape of a trun-cated sphere. The flux residue is cleaned off, if necessary, and the result is a wafer of solder bumped chips.
Electroplating Solder System
The fundamental design and operation of an electroplating cell is reviewed in Figure 3. An electroplating cell consists of two electrodes immersed in an electrolyte and connected to a power supply. The electrolyte is the conducting fluid that allows the transport of ionized atoms and molecules between the anode and cathode. On the power supply side of the two electrodes, the transport is by electron current. At each electrode, oxidation or reduction reactions take place. The cathode supplies electrons to reduce the positively charged metal ions from the electrolyte, which then plate the conducting surface at this electrode. The anode accepts electrons to oxidize the metals, converting them to positively charged ions in the electrolyte.
The anode may be a consumable or inert metal. Using an inert anode requires periodic additions of metals to the electrolyte to replace those plated onto the cathode. This requires frequent plating bath analysis and replenishment. A consumable anode is composed of the metals that are being plated. In the case of solder, the anode is composed of the alloy composition targeted for plating. The metals depleted from the electrolyte by plating at the cathode are replaced from the anode. The stability of the concentration of metals in the electrolyte is greatly extended with the use of a consumable anode. This reduces the frequency of analysis and replenishment of the metal components of the plating bath.
 Figure 2. Solder bump process flow for both mushroom plating and in-via plating. |
Lead with low alpha particle emission rates is available for anode materials and plating bath components. The anode composition and purity is well controlled with current materials and manufacturing technology.
A typical electrolyte is composed of acid, metals combined with an acid (complexed), water and organic grain refiners. For wafer-level processing, the bath is recirculated, filtered and temperature controlled; this maintains uniform conditions and purity in the plating cell. It is usually filtered in the 2 to 10 µm particle size range, depending on the application. Bath chemistries with lead are commercially available and some proprietary modifications are currently in use. Lead-free baths are under development with promising manufacturable results for the tin/silver and tin/copper compositions.
The cathode is the wafer. More specifically, for patterned wafer plating, it is the exposed seed layer. This is the top conductive layer of the UBM exposed by the via in the photoresist. The electron current flows through the ring contact at the outer circumference of the wafer through the electrically conductive seed layer to the base of the via. There the electrons combine with the metal ions at the plated metal interface.
Wafer Edge Contact Issues
Electrical contact at the wafer edge is made by a ring assembly that holds the wafer, provides contact to the seed layer metal around the full circumference of the wafer, and seals the contact from the electrolyte. This is a radially symmetrical system, so it is important that the electrical contact quality is high and uniform around the circumference so as not to induce resistive variations in the current flow through the seed layer. A photoresist edge bead removal (EBR) region is processed to expose the seed layer along the outer edge of the wafer, outboard of the die to be plated.
 Figure 3. Electrochemical deposition (ECD) cell for patterned plating of metal. |
The sealing component of the ring contact assembly isolates the electrical contact region by sealing against the photoresist or the seed layer metal just inboard of the electrical contact. If the contact and seed layer are exposed to the electrolyte, they will also become plated with solder. This is undesirable for two reasons. The maintenance or exchange frequency of the electrical contact may be too high for a production process. The plating at the edge of the wafer, in the EBR region, represents an uncontrolled plating area and negatively impacts bump height process control and cross-wafer uniformity. Some designs for ring contacts intentionally seal on the seed layer just outboard of the photoresist edge, thus allowing an annular region to plate with solder. This approach is still debated regarding the impact on plating uniformity, process control and the effect of a ring of solder around the edge of the wafer on subsequent process steps.
Electroplating Solder Process
Patterned plating – electrochemical deposition within the photoresist-defined pattern – begins with a pre-wet step. The pre-wet chemistry may be water or a dilute acid, and a surfactant may also be used. When any material beside water is used, a concern arises about transferring the pre-wet chemistry into the plating bath; this is most easily resolved by using the same components that are in the plating bath to make up the pre-wet chemistry.
The pre-wet step serves multiple purposes. When oxidation of the seed metal at the base of the via is present, the pre-wet is used with an acid to remove the oxidation that would otherwise be a barrier to electrodeposition of the solder. Wetting the via helps the initiation of plating by improving the efficiency of the metal ion transport to the surface of the seed layer. Pre-wet processing usually employs direct impingement to the wafer surface, as with a spray, to displace the air with the chemistry at the base of the via.
The rate of electrochemical deposition is fundamentally dependent on the rate of charge transfer between electrodes. The concentration of metal ions in the electrolyte and the temperature play stronger roles when mass transport is the primary mechanism for deposition rather than charge trans-port. While the bath composition and temperature are main-tained, the primary factor to control is charge transfer at the plating surface. The current density is the operative term because both the rate of charge transfer and quantity of charge across the plating surface determine the rate at which the metal deposition takes place.
The current density and the electric field are dependent on anode design, plating chamber design and the shape of the cathode. The cathode electrical terminal is the seed layer, and the plating mask is directly between it and the anode. The ideal plating system is designed to produce a flat equipotential pro-file at the plating surface, so that a uniform current density is available at the plating mask. The plating current is “funneled” through the vias in the photoresist mask. A properly designed plating system provides the means to adjust the shape of the equipotential surface at the cathode (wafer) in order to com-pensate for systematic non-uniformities at the plating surface.
Process Integration
Some of the main factors affecting the uniformity of plating within all the vias on the wafer are the uniformity of the conductive properties of the seed layer, the consistency of the size and shape of the vias in the photoresist, and the relative density of plating area across the wafer. The seed layer, which is usually applied by sputtering, is the top layer of the UBM stack. The seed layer provides the wettable surface for the solder and an even and low resistance terminal for the cathode of the plating cell. The resistance of the seed layer needs to be much less than the resistance of the electrolytic cell so that its impact on current distribution is negligible. This material plays a key role in the adhesion and reliability of the solder bump, so the purity of this layer is important to maintain. Current sputtering technology is providing the necessary process quality and control for this application.
The photoresist plating mask process contains a multitude of factors that can affect the quality of the solder bump. All of these factors are controllable for manufacturability as demonstrated by current production results. Some of these factors are specific to patterned plating and the rest are conventional photomasking process control issues.
The ideal profile for a via, from the standpoint of controlling current density, is a cylinder. Because the cross-sectional area of a cylinder remains constant as you move up in height, the power setting may deliver a single, constant current that will maintain the current density for the entire plating recipe. More typically, however, the sidewalls of the vias have a slight taper, being larger at the top. In this case, the plating surface area increases gradually as the via is filled, requiring an increasing current to maintain a constant current density. This is accomplished by stepping up the current through the course of the plating recipe or by ramping the current over time. The key control point for the via profile is to produce a uniform shape all across the wafer. Closely related to this processing issue is the need to keep the dimensions of the base of the via constant across the wafer. This involves the exposure, development and curing of the photoresist as well as keeping the base area clear of photoresist residue.
 Figure 4. Three different shapes of plated solder with the same volume of material. |
The fundamental goal of solder bumping is to plate a target volume of material that will produce a specified ball height after being reflowed. If the desire is to deposit all of the solder within the photoresist, which would seem to allow more control over the volume, a taller photoresist layer will be needed. The tradeoff with this approach is the difficulty with applying the thick layer and maintaining dimen-sional uniformity of the vias across the wafer. Relatively small height variations that do not affect dimensional control of the vias are acceptable because the total height will not come into play in the plating process. Development of thick (more than 100 µm) liquid photoresist is progressing and showing some prom-ise. If a smaller photoresist thickness is used, which affords better thickness con-trol as well as easier patterning uniformi-ty and clearing of the base of the vias, the solder must be plated above the top of the photoresist. (This is called overplat-ing or “mushroom” plating.) As the sol-der builds up above the photoresist, it spreads out laterally and forms a bump in the shape of a mushroom. This method is also used in manufacturing and is shown to produce uniform and controllable solder bump heights. Figure 4 shows how the progression from a cylindrical via to a tapered via to mushroom plating results in smaller plated bump height, and therefore, shorter plating times. These dimensions produce equal volumes that reflow to the same bump height.
One additional concern with mush-room bumps can be a difficulty with clearing photoresist or UBM next to the base of the bump in the subsequent strip and etch steps. Manufacturable wet processes for photoresist strip and UBM etch have been shown to alleviate this concern.
Via Sidewalls
The earlier discussion on pre-wet focused primarily on wetting the seed metal at the base of the via. It is important that the sidewall of the via also wets properly so that the mass transport between the plating surface and the bulk of the electrolyte is not significantly reduced during the plating recipe. Additionally, proper wetting ensures that a gap does not form between the photoresist and the side of the solder bump as it plates vertically, which would reduce the total volume of solder deposited during the recipe.
A conventional photoresist ashing process is sometimes used before electro-plating, which re-conditions the surface, making it more easily wettable by the electrolyte. Improper baking or curing of the photoresist may result in a leaching or diffusion of material from the resist into the plating bath. This causes imme-diate problems with plating along the sidewall of the via. Long-term problems arise with the changing composition of the plating bath because of incorporation of this unwanted material.
Bump Height Uniformity
The uniformity of bump heights within a die (coplanarity) is the most critical plating performance metric. The range of bump heights within a die determines how reliably the chip will connect with its substrate. The within-die uniformity is not easily adjusted in the plating process and is mostly dependent on the layout of the masking pattern. The local via density modifies the current flow in the immediate area with high-density areas plating at a slightly lower rate than nearby lower density areas. This may be thought of as a localized, non-uniform distribution of plating current. The spacing between die on the wafer also comes into play with this effect especially with very high density bumping patterns. Practical experience has shown that, even with large variations of bump density within die layouts, the coplanarity for electroplated solder bumps in properly designed plating cells is well within the technological requirements. As the technology evolves and densities increase, more attention is paid to bump layouts to account for this effect. Improvements in the design of within-die bump layouts, wafer layouts and plating cells have resulted in better bump height uniformity.
The uniformity of bump heights within the wafer is important for the basic stability of the die-to-die bump height. This is the primary measure for electrochemical deposition systems to deliver manufacturable wafer level processing. The addition of dummy or sacrificial bumps between the outermost die and the edge of the wafer is being used to improve the across wafer bump height uniformity.
After solder bumps are plated, rinsed and dried, it is time to strip the photoresist. This is straightforward with conventional liquid resists, even when they are relatively thick. Dry resist layers are also being used to achieve a 100-µm thickness range, and these present more difficulty with stripping. The issue is simply to remove all of the photoresist since the next step is UBM etch. There are no serious issues with current technology for stripping photoresist, although more cost and time efficient processes are always desirable.
The UBM needs to be entirely removed from the field areas between the bumps. Because the size and height of the reflowed solder bump is dependent on the area of the wettable metal base, the undercut of the UBM because of etching is very important to control. Current targets are for a maximum undercut of 2 µm. Various etch processes have been demonstrated to deliver less than 2-µm undercut. Another issue with UBM etch using wet chemistry is the undesirable attack of the solder metals by the etchant.1 Multiple processing solutions have been demonstrated to alleviate this problem and are currently being used in manufacturing lines.
Conclusion
Extending wafer-level processing to deliver a WL-CSP is an attractive solution for packaging applications. By leveraging the mature front-end manufacturing processing knowledge from the wafer fab, wafer-level processing is delivering product from manufacturing lines around the world. An overview here of the process integration issues has shown them to be understood and manageable and, to a large extent, variations on related front-end processing issues. The economy of scale applied to processing at the wafer level is a powerful driving force for packaging applications. With advancements in board, materials and wafer-level testing technology, WL-CSP will constitute a growing segment of the packaging world. AP
Reference
- M. Bent and G. Solomon, “Using Wet Chemistry for Etching Under Bump Metal,” Solid State Technology, pp. 89-92, October 2001.
Gary Solomon can be contacted at 712 Mountain Meadows Road, Kalispell, MT 59901; 406-755-2799; E-mail: [email protected]. For information about Semitool, contact Paul Siblerud, Semitool, 655 West Reserve Drive, Kalispell, MT 59901; 406-758-7509; Fax: 406-257-2356; E-mail: [email protected].