STMicroelectronics’ CMOS teams recieve awards

Nov. 29, 2001 – Geneva, Switzerland – STMicroelectronics’ advanced CMOS development teams headed by Thomas Skotnicki at its Central Research & Development facility in Crolles, France, have received two awards granted by the semiconductor and solid-state physics community: the Paul Rappaport Award for the best IEEE paper in 2000 and also the Best Paper award for the ESSDERC 2000 conference, held in Cork, Ireland, in September 2000.

The IEEE award was won for the paper entitled “Silicon-on-Nothing (SON) – an Innovative Process for Advanced CMOS”, which described a new CMOS device architecture developed by a joint team, based in Grenoble, France, from ST and France Telecom. The SON process allows extremely thin (a few nanometers) buried dielectrics and silicon films to be fabricated with high accuracy within the methodologies of conventional epitaxial technology. This characteristic positions it as a leading candidate for future SoC technology where ever-increasing levels of system integration must be achieved with processes that are compatible with spiraling high-volume/low-cost manufacturing constraints.

The IEEE’s Paul Rappaport award will be presented at the International Electron Devices Meeting, in Washington D.C., where ST will present a paper that unveils a small manufactured NMOSFET operating at room temperature within the conventional CMOS process.

ST will describe a poly-Silicon/Germanium notch technique, which enables it to achieve a 16nm gate using conventional lithography.

The ESSDERC award was for the paper entitled “Dielectric Pockets – a New Concept of the Junctions for Deca-nanometric CMOS Devices”, which reported an advance in deep-submicron CMOS technology achieved by a joint ST/France Telecom research team. This paper described an advance in semiconductor technology which overcomes many of the shortcomings of previously described strategies for tackling the SCE (Short Channel Effects) problems that chip manufacturers face in trying to develop processes that can shrink the dimensions of transistors.

Dr. Skotnicki, a senior member of the IEEE and fellow editor of the IEEE Transactions on Electron Devices, is an expert in MOS technology, in which he has worked for over 20 years. A graduate of the Warsaw U. of Technology, Poland, he joined France Telecom R&D in 1986, where he first worked on CMOS devices and modeling. In 1999, he joined the STMicroelectronics Central Research and Development team at Crolles, France, where he now manages the Advanced Devices Program. He holds more than 30 patents and has authored over 100 papers in the field of electronics.


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