Intel packaging technology aims to enable 20-GHz processors by 2006

SANTA CLARA, CALIF. – Intel Corp. recently announced that it has demonstrated a new packaging technology that could enable the development of 20-GHz microprocessors by 2006 or 2007. This packaging technology, called “bumpless build-up layer” (BBUL), uses a proprietary bumpless-bonding manufacturing process that could enable a one-billion-transistor processor at a thickness of only 1 mm. Intel claims it has developed chips based on its BBUL technology in the laboratory but has no plans to announce a chip based on this technology until 2006 or 2007.

This technology could pave the way for “system-in-a-package” products, enabling a new class of devices. With BBUL, it may be possible to develop mobile, embedded computer devices that can be used to transport data to and from a home, car and office.

BBUL differs from conventional chip-packaging processes in that it makes use of built-up layers and consists of only two layers – the device and copper interconnect. With this technology, the silicon is embedded in the package core and only the lower interconnect layer needs to be built up, according to Intel.

Also, BBUL does not require C-4 bumps or a top interconnect layer. However, there is still a need for the bottom interconnect layer, which attaches the pins to the board.

Analysts are encourage by Intel's foray into bumpless bonding. Jan Vardaman of TechSearch International (Austin) said, “A lot of people have been working on bumpless bonding for some time. What Intel is describing sounds pretty significant.”

The challenge is that this technology has traditionally been too expensive for commercial markets. General Electric, NEC and others have tried to develop bumpless-bonding technology for military applications but have been held back by the cost barrier. Analysts are hopeful, however, that if anyone is capable of bringing this technology to market, it's Intel.


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