International SEMATECH Takes Delivery of SEZ Spin-Processor for 300 mm R&D

December 4, 2001 — VILLACH, Austria — International SEMATECH (ISMT) will take delivery of the 1300 SEZ Spin-Process tool for its 300 mm silicon wafer research and development, according to the SEZ Group. Based on previous success using SEZ tools for other frontside and backside applications, ISMT plans to use this tool to develop process modules for double-sided pre-oxidation and pre-gate cleanings.

The 1300 system is a single-wafer processing machine used for double-sided wafer treatment. It is designed to provide repeatable wafer processing simultaneously on both sides of the wafer. The tool is able to use up to two different chemicals in programmable sequences to process wafers in a single process cycle, with an additional DI water or ozonized DI water rinse and nitrogen dry. Al of the chemicals can be drained or recycled within the system, reducing consumables and significantly lowering cost of ownership.

“Demand for SEZ’s innovative single wafer process technology continues to be strong, especially with the adoption of 300 mm technology,” said Kurt Lackenbucher, chief marketing officer of the SEZ Group. “With the move to large wafer chip production anticipated to offer 25-35 percent cost savings as chipmakers increase substantially the number of die produced on these large wafers, it is encouraging to see R&D activities continuing in full force for cost-effective 300 mm cleaning processes.”

In May, SEZ America implemented an R&D department in the U.S. to help develop new projects and products in close collaboration with its U.S.-based customers. The company created the department in response to the growing need of its U.S. customer base for strong, local development and engineering projects.

The 1300 tool is a smaller version of the SEZ Spin-Processor 8300. The 1300 has one process chamber, while the 8300 contains four process chambers. The 1300 is appropriate for ISMT’s needs, given limited cleanroom space and modest volumes of wafers. Installation is scheduled for December 2001.


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