SIPs at forefront of KGD Packaging and Test Workshop


Editor's Note: Advanced Packaging was traveling on September 11 to cover the Known Good Die Packaging and Test Workshop. We had to return home, but Larry Gilg of the Die Products Consortium, one of the conference organizers, kindly volunteered to report on the event for our readers.

There was something for everyone at the Eighth Annual International Known Good Die (KGD) Packaging and Test Workshop held in Napa, California. In addition to the traditional emphasis on KGD test and reliability conditioning for ICs, this year's workshop included analyses of worldwide markets for die products, technologies for implementing systems in a package (SIP) using die products, as well as techniques and strategies for substrate and finished module testing.

The workshop attracted international participation with 90 attendees from 61 organizations and 20 exhibitors of equipment, materials and supplies.


The message delivered at the workshop was about SIP technologies being adopted by IC packaging houses and contract electronic manufacturers worldwide. Electronic manufacturers, such as Amkor, ChipPAC and SPIL, have invested in the capability to assemble multi-chip packages that contain one or more bare die as well as discrete components on a high density interconnect. Plans for applications of this technology are being developed by OEMs worldwide. The issues of mounting technology, test and inspection strategies and mixed technology manufacturing methods were all addressed in the 36 technical presentations during the three-day workshop.

SIP assembly methods can take advantage of flip chip mounting of high pin count ICs to achieve high performance. Bumping services are becoming more widespread and costs are coming down, according to Jan Vardaman, president of TechSearch International. This is enabling the market for watch modules, automotive controllers, pagers and disk drive applications to use flip chip mounting for economical SIP implementation. Furthermore, contract electronic manufacturers and IC packaging houses are installing capability to offer “turn-key” flip chip solutions, including bumping and flip chip assembly, along with more traditional surface mount assembly processing, according to Andrea Chen, technical marketing manager for Siliconware USA, Inc.

Chip on Board

Of course, there is still plenty of life left in wire bonding technology for chip on board applications. In a half-day tutorial, Tetsuya Onishi gave an in-depth description of wire bonding technologies, as well as information on the burgeoning markets for this technology in Asia. These markets are in the low-cost product space, where mounting bare die directly to laminate substrates offers the lowest cost assembly method available. Onishi provided a checklist of issues to address when mixing wire bond assembly with traditional solder reflow for surface mounting technology. Practitioners must keep in mind the different requirements for cleaning, reflow temperature, PCB warpage, contamination and solder printing when designing a process that includes both wire bonding and SMT.

Test and Reliability

The fundamental issues of test and reliability assurance of the unpackaged IC itself have critical importance to companies that implement SIP technologies. Again, practitioners are able to take advantage of a growing trend in the industry for the IC manufacturer to perform more and better tests at the wafer level. Art Wager, formerly with IBM and now a reliability consultant, described wafer-level test methods and reliability screens that are aimed at eliminating or reducing the amount of ICs needing burn-in. Using a test regime of extremely low voltage tests, high voltage stress, functional and Iddq testing to identify outliers, companies can understand and control the quality and reliability of the product shipped without necessarily requiring burn-in of entire manufacturing lots.

There were several presentations on wafer-level burn-in (WLBI). This technology has been reported at the past several KGD workshops as a “future trend.” However, presentations from Aehr Test Systems (Fremont, California) and Motorola (Austin, Texas) indicate that this technology is now in production at several manufacturing sites. WLBI is not a solution for all die products, but these recent reports show that one more barrier to adoption of die products has been scaled.

Looking Ahead to 2002

Next year's workshop will held September 8-11, 2002, in Napa, California. More information is available at To obtain a CD-ROM of the workshop proceedings, please contact Larry Gilg (tel: 512-452-0077; E-mail: [email protected]).



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