By Ruth DeJule
Increased complexity and functionality in semiconductor devices has placed a greater emphasis on interconnects, where delays have become one of the most significant factors affecting chip performance.
Efforts to minimize interconnect delay have largely concentrated on new process technologies such as dual damascene, and new materials, such as copper and low-k dielectrics, rather than on the physical layout.
Today, sophisticated computing resources and innovative development efforts have given rise to a fundamentally different approach to interconnect design, the X Architecture. Jointly developed by Toshiba Corp., Tokyo, Japan, and Simplex Solutions, Sunnyvale, CA, this architectural approach uses diagonals to shorten interconnects. Ultimately, this could mean smaller, faster devices with decreased power consumption.
For the past 20 years, chip design has been primarily based on the “Manhattan” layout, an architecture built on right angles.
X Architecture uses diagonals.
In complex, multiple-metal-layer devices, the primary direction of the interconnect can be rotated on the fourth and fifth metal layers by 45 degrees, enabling a reduction in total wiring on the chip by more than 20%. Based on Simplex’s “liquid routing” technology, wiring can be routed in eight directions (four diagonal and four Manhattan), on every layer. Therefore, a more direct connection between any two transistors can be established, regardless of their proximity to one another, thus minimizing wiring on the chip.
Initial evaluations indicate that this wire-length reduction will enhance chip performance by 10%, decrease power consumption by 20%, and result in 30% more working chips on a wafer, said Jan Willis, VP of business development at Simplex and steering group facilitator of the X Initiative, a consortium formed to build an infrastructure.
There are currently 23 member companies, spanning the entire design-to-silicon infrastructure: semiconductor intellectual property, electronic design automation, design services, photomask production, semiconductor equipment and IC manufacturing.
A milestone was reached in October when DuPont Photomask successfully produced the first X Architecture mask, using existing photomask production equipment, for 0.18-micron process technologies. According to DuPont, all test results fell within the range of normal of traditional mask designs. This was a combined effort using Simplex Solutions’ design data in GDSII format, Numerical Technologies’ CATS mask data-preparation tool to fracture the data and efficiently process the X Architecture geometries, Applied Materials’ Etec Systems division’s ALTA 3700 laser mask pattern generation system to write the mask, and KLA-Tencor’s 363 UV inspection system to inspect the mask.
This use of current equipment in implementing the X Architecture onto masks is particularly encouraging. To make it production worthy, the X Initiative will continue to focus on removing barriers to adopting this new approach to interconnect design.