Die Traceability

Upgrading strip and wafer-level packaging


Strip packaging and wafer-level packaging (WLP) are now making packaging and final test more like fab processing. That is:

  • Strips and wafers are “standard” substrates, like the wafer is in fab.
  • A packaging process is performed simultaneously across strips and wafers rather than sequentially or on separate units. Fab processing is typically at the wafer level.
  • Wafer and strip IDs are available to trace substrates through packaging and test. This is similar to the approach used in modern wafer fabs.
  • Substrate or strip maps enable die traceability to a site. This is similar to the wafer maps used in fab for tracking process results to wafer sites.

Three reasons for using die trace are to improve yields through packaging and test, tie back-end test results to fab processing, and isolate problems that occur when the product is in the field.

Elements of Die Trace

There are two primary elements for implementing a trace system for any item. The first is an identifier (ID), which is typically a number or a mixture of numbers and alpha characters. This ID is conceptually similar to a driver's license number or a tracking number used by package delivery services. The second item is a map that tells us where items are given their identifiers. There may be only one item in a map, as there is when a die has an ID. There may be an array of items in a map, as there is in a strip or tray. The map is typically kept in a computer database. These two elements will be discussed as they relate to trace in strip packaging and WLP.

Substrate IDs

Strips and wafers can be considered as substrates for carrying die through the packaging and test process. The semiconductor industry, through Semiconductor Equipment and Materials International (SEMI), provides trace ID standards for both of these types of substrates.

Figure 1. Package strip with ID mark.
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Strip IDs: The strip ID is a relatively new standard from SEMI. The standard is T9 and defines 22 characters in a 2D data matrix code (usually, it takes 7 to 10 bits to make one character). It is typically laser-scribed onto the surface of the strip. The location of the ID is not specified, to allow maximum usage of the strip area. Figure 1 shows a strip and ID mark placement on the strip.

Wafer IDs: A wafer ID is available on a wafer as it comes from fab into wafer test. There are a few SEMI standard markings to fit different wafer conditions. Standard T2 defines a 2-D code for the wafer ID. The ID is used at wafer test during testing for good die to tie the wafer ID with the wafer map generated by the wafer prober. The wafer map is used to transfer the good die onto strips at die attach. A new strip map can be generated at die attach and uploaded to a factory computer. Now the strip ID is linked back to the wafer ID for traceability.

Substrate Maps

The use of strip and wafer IDs enables maps of strips and wafers to be available during packaging. Each substrate has a map that is found from its ID. Substrate maps are stored in a computer database. When a substrate enters equipment, the ID is read, the equipment requests the map associated with the ID, and the map is downloaded to the equipment from the factory computer (Figure 2).

Figure 2. Mapping sequence through equipment.
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The map information has two sections. One, a header, provides “bookkeeping” information about the map. This typically includes such information as the equipment that generated the map, the date, and the map organization. The other section is the map itself, typically in row and column format.

Strip Map: Currently, the information on the strip map is defined by SEMI document 3154A. The strip map is going to be published as a SEMI standard. The standard covers the strip map, updating the map, and how it is transferred between manufacturing equipment and the factory computer.

Wafer Map: Wafer maps, also called “sort maps,” are widely used between wafer test and die attach to transfer the good die locations on a wafer to the die attach equipment. These maps can be used in WLP. For example, the map is used during inspection such that only electrically good die are inspected. At solder ball inspection, the wafer map is used to inspect good die. If the inspection fails, the wafer map is updated. The updated map is then available to the next piece of equipment in the manufacturing flow.

SEMI Standards document 3265A defines the data in the wafer map, and document 3157A defines the map data format.

Other Trace Methods

In addition to substrate IDs and maps, die tracing between wafer test, final test and the end product can be provided by a 2-D mark on the die and or a circuit on the die. The 2-D backside mark is appropriate to use for tracing when the back of the die is available to a vision system. Figure 3 shows a laser mark on the back of a die that includes product and trace information. SEMI has a taskforce working on a die backside trace mark. Use of a circuit for die tracing is a more flexible method because it allows traceability independent of the packaging and bonding method. The ID circuit is read out at wafer test and stored along with the die location from the wafer map. It can be read out at future steps with a tester, even after the die is placed on a board

Implementing a Die Tracing System

All of the required resources for implementing trace in strip or WLP are currently available, but they need to be brought together for implementation. Some equipment suppliers are tying together the combination of equipment and software for using strip maps through packaging, test, and placement into shipping media.

An organization may choose to implement trace with a mix of equipment. If so, the resources that may be needed are:

  • A database for managing information on IDs and maps
  • A marker for putting IDs on the back of die
  • ID readers for strips, wafers or die
  • Equipment that supports transfer and updating of maps
  • Engineering services for resource integration.

The packaging equipment that needs to support die tracing are those tools that process by site, such as die attach and inspection, lead bond and inspection, ball placement and inspection, laser mark and inspection, and test handlers.

Examples of Die Tracing

Strip-level maps with trace information enable concise feedback from test to packaging. Because the site on the substrate is known from the map and the substrate history is known from the substrate ID history, packaging induced failures can be isolated to particular equipment and substrate locations.

Figure 3. Die backside mark.
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Die-level trace allows a manufacturer to tie the semiconductor fab and back-end test together. After packaging, test results can be correlated to a wafer and to the site on that wafer. For example, a final test lot may have a number of parts with voltage margin failures. When there is traceability, it can be determined if the parts all came from the same wafer and even the same area on a wafer. This would be valuable information for solving a wafer fab problem.

In one published result,1 die traceability enabled reduction in early life failures of an IC. By using tracing information, it was found that certain areas of wafers were producing more reliability failures than other sections. The source of the failures was determined to be in a fab processing step, so process engineering fixed the problem, preventing further contamination of production parts.

Die traceability also enables quick analysis of systematic problems found in the end product associated with a semiconductor device. Die tracing on a board is done easily with a circuit on the die. The trace circuit is read out during board test, and the ID is matched against a database. The matching ID in the database is also the address for the trace information. It can be quickly determined if the source is a site, area, wafer or lot level problem.

Figure 4. Preferred trace method for different spans in a manufacturing process.
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Board and field problems can be very expensive to the user and the manufacturer of semiconductors. A semiconductor product in a board that causes the board to fail its test will cause the board to be reworked or scrapped. If the board fails in the end product, the product is returned and failure analysis is done. Die tracing mini-mizes the number of recalls by isolating the problem source to specific components.

Status of Die Traceability

Die tracing is being implemented in selected situations. An example is backside marking on chips being used in multi-chip modules. Die tracing is also used in high-end semiconductor devices to gain the last few yield points, and to prevent remarking to higher grade parts by black-market resellers.

There are map-based trace systems implemented in strip packaging and test lines. Strip maps enable parallel testing of components, so during testing, the device grades and good/bad results are mapped. After testing, the devices are singulated and picked by site to go into different product grades (or the reject bucket).

Figure 4 shows the preferred trace method for different spans in the IC product manufacturing process and for IC components on boards. Maps are preferred between strip packaging and test because both are done in the same format. A circuit is preferred for tracing back from test to wafers since the die ID is known to the test equipment at both locations. A circuit-based trace is also preferred for multi-chip modules when the chip ID can be read out during module test. AP


  1. Walter Riordan, Proceedings of the International Reliability Physics Symposium, 1999, pp. 1-11.

Jerry Secrest, principal consultant, can be contacted at Secrest Research, 250 Willowbrook Drive, Portola Valley, CA 94028; Tel/Fax: 650-851-8142; E-mail: [email protected].


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