By Pieter Burggraaf
WaferNews Technical Editor
Looking for an application that will bring the IC industry out of its current slump? Consider the projected growth of broadband and in particular the microelectronics necessary to establish “residential gateways” and “simple to use home networks.”
“Estimates show broadband use growing worldwide from 12 million users in 2000 to 90 million in 2003,” said engineer Johan Danneels from Alcatel Microelectronics, Brussels, Belgium, speaking at the 2001 IEEE International Electron Devices Meeting (IEDM), held late last year in Washington, DC.
Associated with this, fiber optics connections are doubling every nine months, but the last mile, which includes residential gateways, is the bottleneck to greater broadband use. Residential gateways are needed to manage shared Internet access for what Danneels eventually sees as “pervasive computing” — where a user is surrounded by computing devices (i.e., web pads, e-books, PDAs, set top boxes, personal video recorders, IP phones, game consoles, etc.) and smarter kitchen appliances.
“Today, we still think of an Internet appliance as a stripped down PC, but over time even a dishwasher will become a simple Internet appliance that connects to a manufacturer’s site for maintenance needs. In the near future in a home, more money will be spent on electronics than on stoves,” he said.
Danneels believes that deep-submicron CMOS — not emerging alternatives that target replacing CMOS — and first-time-right SoC designs are essential to achieve residential gateways at the right consumer price and with the ability to hit market windows. “Standard CMOS is the only way to drive cost down quickly and aggressively, which are absolute musts,” he said.
In addition, SoC semiconductor companies must master digital, analog, RF, and high voltage designs. Successful companies must rely on third parties — he sees mega-fabs of today’s silicon foundries, as well as research institutes, playing a large role in providing design and process technology needs.
—- CMOS milestones —-
Presenters at 2001 IEDM revealed significant milestones in continuing conventional CMOS transistor technology and advances in associated wafer processing skills. However, a noticeably smaller audience of about 900, compared to 1,700 in 1999 (Washington, DC) and 2,300 in 2000 (San Francisco, CA), attended this key confab. According the IEDM General Chair, MIT’s Judy Hoyt, low attendance this year was due to travel budget cuts, but also current international sensitivity to traveling to the US capital.
Many attendees who did attend directed their attention to low-k and high-k materials issues associated with the relatively short-term continuation of CMOS technology.
—- Low-k technology —-
The continued development of copper low-k processing for advanced CMOS is focused on reliably applying yet softer “ultra-low” <\<>2.3 dielectric-constant materials:
* A large team of engineers at International SEMATECH, Austin, TX (including engineers from TI, Motorola, IBM, and others), is addressing the propensity of porous candidate materials not to maintain mechanical strength and adhesion through CMP processing and k <\<>2.3 after integration. Work at International SEMATECH has also shown a degree of incompatibility with DUV photoresist, which is suspected due to etch and ash processing using nitrogen. International SEMATECH engineers have seen results with “one spin on porous silica material” that maintains its ~2.3 k value after integration.
* Engineers from TSMC, Hsinchu, Taiwan, and Sony, Tokyo, Japan, separately have succeeded in incorporating electropolishing as an alternative to CMP thus allowing use of mechanically weaker low-k materials in four-level copper low-k interconnects. At TSMC, for example, this process has achieved production yields, compared to a process using conventional CMP, on 4Mb SRAMs.
* Other work at International SEMATECH (in conjunction with Infineon Technologies, Munich, Germany; Philips, Eindhoven, Netherlands; and Novellus Systems, San Jose, CA), engineers are investigating the interaction between porous low-k materials and CVD barriers, especially diffusion of CVD precursors into the pores of the low-k material and subsequent metal deposition inside the low-k material. While still needing more complete characterization, the International SEMATECH based group has seen positive results with a novel 5nm thick TiN(Si) copper barrier used with JSR KLD 5109 ultra low-k material.
* Engineers at Hitachi, Tokyo, Japan, have developed the processing necessary to integrate Dow Chemical’s SiLK ultra low-k material with a SiCN barrier, overcoming high capacitance problems associated with using SiN.
—- High-k dielectric —-
Emphasizing the crucial importance to the future of CMOS for developing high-k and metal gate technologies, IEDM included two sessions on this timely topic. While development work continues with zirconium silicates and other alternative such as lanthanide oxide Pr 2 O 3 (Kwangju Institute of Science and Technology, Korea) and Ru<->x<->Ta<->x<-> films (North Carolina State U.), a significant portion of the development activity here is building around hafnium oxide (HfO2):
* Motorola, Austin, TX, engineers have fabricated polysilicon-HfO2 gate-stack MOSFETs, depositing HfO2 at 550 dgC with MOCVD and performing co-silicidation that produces an oxide at the polysilicon interface. This process has produced acceptable NMOS performance, but further work is needed to improve PMOS performance.
* Working with a variation to silicon-surface nitridation (bottom nitridation), researchers at the U. of Texas Microelectronics Research Center, Austin, TX, have incorporated nitrogen in the upper layer of HfO2 via sputtering, resulting in improved and even superior MOSFET characteristics.
* At International SEMATECH, in a comparison of self-aligned MOSFETs fabricated using atomic layer deposited ZrO2 or HfO2 as gate dielectrics and polysilicon as gate electrode, overall transistor characteristics were better for HfO2. Among the advantages were tolerance to a source-drain anneal cycle at 1000 dgC for 10 sec, mobility degradation of ~15%. Further process optimization is needed, however, to improve threshold voltage and drive current.
* A team of engineers from Yale U., Jet Process Corp, New Haven, CT, and IBM, Hopewell Junction, NY, have shown that adding aluminum (Al) to a HfO2 film substantially increases its crystallization temperature; the propensity of HfO2 to crystallize with subsequent processing temperature leads to greater leakage. Specifically, 6.8% Al raises the temperature ~200 dgC and 31.7% ~400 dgC.
The overall message at the 2001 IEDM was that Moore’s Law definitely has life and that fabrication technologies and designs are emerging that will bring the industry to the projected 10nm MOSFET barrier. The beauty of IEDM is that it is also the industry meeting where root sources of eventual CMOS replacement technologies and fabrication diversification for new products emerge.
http://www.wafernews.com