MoSys, Mentor Graphics to deliver BIST for 1T-SRAM memories

Jan. 14, 2002 – Sunnyvale, CA – MoSys Inc., a provider of high-density SoC embedded memory solutions, and Mentor Graphics are collaborating to qualify and deliver memory built-in self-test (BIST) solutions optimized for the MoSys 1T-SRAM family of high-density embedded memories to reduce test cost.

MoSys and Mentor Graphics have verified the integration of 1T-SRAM embedded memories using the Mentor’s MBISTArchitect and BSDArchitect tool suites for memory BIST and boundary scan, respectively.

MoSys and Mentor have formed this strategic alliance to identify and implement new capabilities within the MBISTArchitect tool to test and qualify embedded memories developed by MoSys. The first results of this effort will be available early this year in the form of additional features to support the various 1T-SRAM interface modes. Additional capabilities to support on-chip memory repair analysis for improved yield will follow.


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