By Paula Doe
WaferNews Contributing Editor
Toshiba Semiconductor’s novel plan to rethink the fab to make small runs of systems chips without big capital investment may not be so far out after all.
Tools developed by Toshiba and its partners for such a mini-fab started showing up on the floor at Semicon Japan. Ulvac showed a direct-write ion implanter to cut out resist steps. Tokyo Electron had a scan coater to replace spin coating and CVD, and a flexible thermal processing system to shorten process time to about one hour for most processes.
Such tools will be integrated with near real-time lot management software in a demonstration line at the new Japanese government cleanroom in Tsukuba opening in April. The goal: A low-cost little fab that can quickly turn out small volumes of ever-changing systems chips at a profit. Toshiba figures such a mini-fab could run 100 lots a month using a total of only about 35 specialized production tools, compared to the 70-some tools it now takes to run the same volume using conventional equipment.
By doing ion implantation directly through a stencil mask, Ulvac and Toshiba have said they figure they can eliminate up to 10 rounds of resist coating, exposure, development, and removal for all the different p-n junctions, potentially cutting process time from four hours down to one, and costs in half – and all that other lithography and resist equipment would no longer be needed for ion implantation. Ulvac has worked with its maskmaker to improve mask resolution beyond what it reported at IEDM last year, and worked with Nippon Seiko to improve the accuracy of stage positioning, to get the tool ready for the market.
TEL’s newly announced TELFORMULA thermal processing system has been Toshiba’s mini-fab poster child, a model of all sorts of the properties needed for fast and flexible small lot production. It runs small lots in about an hour, instead of large batches in four or five. It can change the load from one to 25 wafers in a batch without changing the recipe or running dummy wafers. And it uses in situ dry chamber cleaning technology, eliminating the need for off-line wet cleaning, and could potentially be used for multiple processes in succession. The companies have said the furnace heats up at 200 dgC/minute compared to 15 dgC for standard batch tools. TEL says shipments will begin spring 2002.
TEL also has a new approach to coating low-k interlayer dielectric at lower cost with its demonstration scan coater, also developed with Toshiba Semiconductor. By controlling the pressure of the liquid coming through a very fine spray nozzle, and maintaining a stable speed of swing back and forth across the advancing wafer, the coater can make a surface with only 3% variation with the same throughput as spin coating but using only 10% as much material. By eliminating the spun off materials waste it also reduces impurities in the chamber and cuts cleaning solvents and waste liquids. TEL will mount the scan coater it on its existing Cleantrack ACT 8 SOD system. It plans sales by the end of 2002.
Toshiba Semiconductor has also been working with Ebara on developing a low-cost immersion copper plating system, to make a thinner and more uniform copper layer while using only a fraction of the usual plating solution. The tool uses a porous ceramic plate with high resistance, which allows the electrodes above and below it to be brought very close together, so the plating solution bath can be reduced to only about 1mm deep. Cleaning and drying are also done in the same module to reduce process time.
The Japanese government will kick in $33 million (4 billion yen) for integrating these tools into a demonstration line with flexible and almost real-time lot management software under the HALCA project. Consortium members will contribute another $21 million (2.5 billion yen). Participants besides Toshiba, TEL, Ulvac and Ebara include Dainippon Screen and potential users Sharp, Seiko Epson, Sony, and Rohm.