10th Anniversary Insights
The wire-bonding tyranny of “or”


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Many industry luminaries today debate what will be the interconnect technology of choice for semiconductor devices in the future. Is it going to be wire bonding or flip chip? This is a classical tyranny of “or.” Upon reflection and some due diligence, one could actually conclude that the most likely scenario in the foreseeable future is going to be one of wire bonding and flip chip.

Anyone who has been working in the semiconductor packaging industry for any reasonable length of time knows that gold ball bonding continues to be the technolo-gy of choice for chip-and-wire intercon- nect – it is used for more than 90 percent of today's chip interconnect packages. While flip chip is clearly going to claim a certain percentage of the growth in inter-connects because of performance needs that the technology uniquely satisfies, it is evident that the growth in wire-bond interconnects is going to be phenomenal as well. That growth is likely to surpass his-torical trends.

Those in packaging know from early in their careers that given a “choice” between interconnects, wire bonding would be the winner most often, for the overriding rea-son that it is ultimately a lower cost tech- nology. Recall the decade of the 1980s, when wire bonding was supposed to be replaced by tape automated bonding (TAB). Several companies, consortiums and R&D houses had significant and active programs to replace wire bonding with TAB.

TAB was to be the technology of the future. It was stated by highly qualified researchers that semiconductor perform-ance on CPUs and microprocessors would be impeded by wire bonding beyond 10 – yes, 10 – MHz clock speeds. Today, there are processors that are wire bonded and performing in systems at clock speeds nearly two orders of magnitude higher. How does this happen? Where did the scientists go wrong in their predictions? It has to do with a variety of factors ranging from chip architecture to enablers created by the wire-bonding technology itself.

Moore's Law

For a moment, let us review the relevant aspects of the International Technology Roadmap for Semiconductors (ITRS). Table 1 depicts the relationship between silicon feature sizes and pad pitches for both wire bond and flip chip technology. One of the key parameters that wire bonding has enabled is reduction in pad pitch. This has allowed chip designers to scale die sizes in relation to their requirements for reductions in silicon device feature sizes. This has allowed for silicon “real estate” to be optimized by eliminating the situation of a “pad limited” chip, in which the size of the chip is decided by the number of pads and the pad pitch.

Figure 1. The progression of wire-bonding capability has tracked silicon technology.
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Figure 1 shows how wire bonding has kept up with Moore's Law. It is worth noting that technology develop-ment is continuing to remain ahead of the ITRS require-ments. Pad pitch was another reason TAB was pursued in the early 1980s. In those days, when pad pitches were greater than 150 µm and pin counts at or below 40 leads, it was difficult to forecast the capabilities of wire-bonding technology. Ten years ago, an in-line pad pitch of 115 µm was considered to be “fine pitch.” That leading-edge capability quickly changed to 100 µm, and shortly thereafter, 90 and 80 µm. In 1997-98, the state-of-the-art process was qualified at 70 µm, and devel-opment work was underway on 60 and 50 µm pad pitch. A key point here is that all of this has been achieved without compromising throughput and speeds at which devices are bonded. In fact, every new generation of wire bonders has resulted in productivity improvements of 15 to 20 percent.

Integrated Processes

Today, 45 µm processes are entering production, 35 µm is in development, and 25 µm is on the research drawing boards. Through innovative improvements in the wire, capillary, wire bonders, molding process and factory practices, the speed of pad pitch improvement using wire bonding has actually outpaced integrated circuit (IC) manufacturers' roadmap goals. However, going from 45 µm to the targeted 35 µm level will require additional breakthroughs and more effort; simply increasing wire-bonder performance won't allow IC manufacturers to reach that next plateau. Integrated processes – developed in conjunction with suppliers – will become the norm. Convergence of wafer, package and board-level assembly ultimately will be needed as feature sizes decrease below 70 nm. IC manufacturers will increasingly seek suppliers capable of combining substrates, equipment and bonding tools with the ability to test ultra-fine-pitch packages.

It is anticipated that the growth in interconnects is going to be significantly higher for the finer pitches. As an example, the growth over the next five years for greater than 100 µm pitch devices will be in the 8 to 10 percent CAGR range, whereas the growth in interconnects for less than 60 to 50 µm will be in the 50 to 70 percent CAGR range. By some estimates, of the total wire bond interconnects in the years 2005 to 2006, about a third will be at pad pitches of less than 60 µm. This creates a phenomenal opportunity to provide integrated and tuned wire bonding solutions.

Additional Enablers

Besides pad pitch and speed, there are other features enabled by wire bonding that continue to make it an attractive option. Advanced looping capability enables thin packages, stacked die, unique bond configurations that extend several rows deep into the chip, and staggered pad bonding for very high I/Os. An additional advantage of wire bonding is its flexibility. The equipment is not package specific, and the technology is scalable through die shrinks and virtually all package families.

Despite the already vast wire-bonding infrastructure, the demand for new factory space, better equipment and more skilled people to support new processes will continue. New development tools, equipment advances and manufacturing practices will serve as the basis for moving forward in this challenging arena. Engineering modeling has been a useful tool for activity supporting fine-pitch wire bonding process and machine development. Modeling is being taken to a new level as pad pitch approaches 35 µm.

Assembly equipment manufacturers are developing new wire-bonding equipment to improve the robustness of the fine-pitch process. This new equipment minimizes the trade-offs that once existed between accuracy and productivity. For example, the requirements will demand that bond placement positioning systems provide the utmost resolution and accuracy available with no loss in speed. X-Y tables, a critical factor in determining bond placement, are now available with sub-micron resolutions.

Table 1. The International Technology Roadmap for Semiconductors predicts the trends for wire-bonding and flip chip technologies.
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Achieving 35 µm pad pitch processes will require bonding wire diameter reduction. New bonding wire alloys are being developed to improve performance (such as lower loops for BGAs and less sweep during molding for fine-pitch packages). This is of particular importance given the finer wire diameters required to achieve decreased ball size in ultra-fine pitch ball bonding. Ball volume reduction by a factor of 8 to 10 and ball force and ball forma-tion energy reduction will also be important.

Capillary tools will have to be tuned to ultrasonic transducers, and new materials will need to be developed to provide adequate strength for bonding to occur. Additionally, challenges resulting from the use of low-k dielectric materials and other new materials in the chips' structures will have to be overcome.

Wire-bonding equipment suppliers are extending the life of this technology by continuing to develop processes for increasingly complex devices with ever-decreasing pad pitch requirements. Gold ball bonding has come a long way since its inception more than 30 years ago, and it still has a long way to go. Looking ahead, it will be wire-bonding AND flip chip.


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Jack Belani, vice president, marketing, can be contacted at Kulicke & Soffa, 1504 McCarthy Blvd., Milpitas, CA 95035; 408-474-3419; Fax: 408-433-5197; E-mail: [email protected].


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