Meg Villeneuve

SAN JOSE, CA—In the updated International Technology Roadmap for Semiconductors (ITRS), the working partners of the group, including the Semiconductor Industry Association (SIA), say chip feature sizes are shrinking quickly and reports that the 2001 roadmap “calls for more aggressive scaling—making computer chips smaller—than previously planned.”

In 1999, the ITRS called for feature technology nodes to reach 100 nm or 0.10 micron in 2005, with 70 nm in 2008, 50 nm in 2011 and 35 nm in 2014. That's all changed, with the industry expecting to reach 90 nm in 2004, 65 nm in 2007, 45 nm in 2010, 32 nm in 2013 and 22 nm in 2016.

“The scaling of the smallest feature size in integrated circuits—microprocessor transistor gate lengths—shows just six years until it hits some fundamental limits. For example, a gate length of just 25 nanometers is now projected for 2007. This dimension wasn't supposed to be reached until 2013 in the 1999 version of the roadmap,” notes the SIA.

In the report, issued in late November, the SIA and its partners describe the challenges associated with the shrinking technologies in the coming years, including environmental health and safety and contamination-control issues.

When the industry reaches line widths of 65 nm, the roadmap reports the following challenges will affect the contamination-control industry: chemical, materials and equipment management; resource conservation; workplace protection; climate change mitigation; ESH design and measurement methods; patterning, cleaning and filling high-aspect rations features. (To view the entire report visit www.semichips.org.)

A more specific view cites the following issues/needs:

• Develop processes that meet technology demands while reducing impact on human health, safety and the environment, both through replacement of hazardous materials with materials that are more benign and by reducing chemical quantity requirements through more efficient and cost-effective process management.
• Design more energy- and water-efficient processing equipment.
• Increase resource reuse and recycling.
• Increase knowledge base on health and safety characteristics of chemicals and materials used in the manufacturing and maintenance processes, and if the process byproducts; and implement safeguards to protect the users of the equipment and facility.
• As features shrink, etching, cleaning and filling high-aspect-ratio structures will be challenging, especially for low k dual damascene metal strucxstures and DRAM.

The roadmap was developed with the help of 800 participants from the US, Europe, Japan, Korea and Taiwan. “When the 2001 roadmap looks 15 years into the future, the physical gate length is projected to be a mere 9 nanometers. We are beginning to consider technologies beyond planar or even post-CMOS devices,” says Paolo Gargini, chairman of the ITRS and fellow, Intel Corp.