Chartered, Cadence partner for process design kit offering

March 25, 2002 – Singapore and San Jose, CA – Cadence Design Systems Inc. and Chartered Semiconductor Manufacturing are working together to help the mixed-signal market reduce cycle times on designs with new Chartered foundry process design kits (PDKs).

The PDKs will integrate Chartered’s manufacturing processes for multiple nodes — from 0.35-micron extending to 0.10-micron — with the Cadence front-to-back design and verification flow for analog, RF, and mixed-signal ICs. The result is a design-through-manufacture path that helps companies meet aggressive product schedules for advanced mixed-signal SoCs, the companies said.

To introduce the PDKs to the market, Chartered and Cadence will co-host a worldwide seminar series, Acceleration to Technology Access, at the following locations and dates: San Jose, May 7; Irvine, Calif., May 9; Boston, May 14; and Austin, May 16. Locations and dates for international seminars will be announced at a later time.

The PDKs will enable Chartered and Cadence customers to immediately begin designing chips rather than first developing their own required process design kits, the companies said. The PDKs provide a symbol library and technology file for the design automation flow and DRC-correct parameterized cells to automate device generation.


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