Synopsys, ST form partnership to lower cost of test for SoCs

March 6, 2002 – Paris, France – Synopsys Inc. has formed a two-year partnership with STMicroelectronics, Geneva, Switzerland, focused on creating new methodologies and technologies to reduce manufacturing test development cost and effort while simultaneously improving test quality.

This new alliance is to develop and deploy advanced manufacturing test solutions innovated by Synopsys and ST that solve test challenges at reduced costs, and provide turnaround time, and time to market advantages for complex SoC devices.

The alliance will expand on the accomplishments of an earlier ST/Synopsys test partnership — enabling design-for-test closure for SoC design flows — by adding two major objectives: First, the alliance will aim to optimize ST’s design-to-manufacturing test flows to improve turnaround time and time to market; and second, it will strive to enable ST to reduce its manufacturing test costs.


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