10th Anniversary Insights
A short history of wafer-level packaging


There have been only a few fundamental shifts in the history of electronic packaging that changed the whole industry. One was the step from through-hole assembly to surface mount technology (SMT). More recently, the increasing pin-counts forced the development of area array packages, like the ball grid array (BGA). The trend to smaller, lighter and thinner consumer products was only achievable by further miniaturization, which drove the concept of chip scale packaging (CSP). The next step to reduce packaging cost was the approach of finishing the chip package directly on the wafer, and wafer-level packaging (WLP) was born.

The Beginning of the WLP Concept

Packaging technologies are the link between the small dimensions of the integrated circuits (ICs) and the larger dimensions of the printed circuit boards (PCBs). However, the key functions of the package is not only matching the gap between the sub-micron structure sizes of ICs to the PCB dimensions, but also leveling the different coefficients of thermal expansion (CTE) of the organic-based PCB and the silicon to ensure the long-term reliability of the whole system.

In 1994, Mitsubishi Electric Corp. released its new package concept that they called CSP.1,2 In this approach, Mitsubishi used thin-film metallization to reroute the peripheral I/O pads to an area array of solder pads. After singulation, the ICs were encapsulated with a polymeric resin using a base frame. The final step was a stencil printing process for the solder balls. It was neither a chip size package – it was larger than the die – nor a technology that was completely finished on the wafer, but it already had the basic construction for several WLP technologies that were developed years later. The packaging concept was the result of combining the technology of flip chip assembly with SMT and BGAs under the constrain of further miniaturization.

Figure 1. The advantages of BGA/CSP, flip chip and the economics of wafer processing are combined in WLP technology.
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A different approach released in 1994 was developed by ChipScale: the MicroSMT package. This technology was a real WLP process.3 Its package was based on thin Au beams that connected the die bond pads with peripheral metallized silicon posts formed by Si etching in the dicing streets. The final step before singulation was plastic encapsulation, which was necessary because the assembly was a face-up process. The drawback of this technology was the requirement of wide saw streets and process steps that were used in the MEMS industry but not yet common in the packaging industry.

Around this time, a popular idea was that the single chip package had to be completed and tested directly on the wafer. After singulation by dicing, the die should be ready for the assembly in a flip chip fashion using high throughput SMT lines. These wafer-level packages would be real chip size (rather than chip scale) packages because of the wafer-level processing. The unique feature of this wafer-level approach for CSPs is that there is no bonding technique inside the package. The advantages of BGA/CSP, flip chip and the economics of wafer processing would be combined in a low-cost packaging solution (Figure 1).

The First Wave: Redistribution

In 1995, Sandia National Laboratories published its redistribution concept, which was based on a Cu/polyimide process.4 The technology was the result of having tight peripheral pad pitch on the IC. Because of the rapid improvement in wire bonding, the pad pitch of all different kinds of ICs was reduced dramatically. The issue of a “pad-limited” chip was nearly solved. The die size was not the result of the limitation of wire bonding technology anymore. The classic flip chip was now confronted with this narrow pitch, which is not a problem for bumping but more for assembly and PCB technology. The solution to this issue was the introduction of “redistribution.” A thin-film process is used to reroute the peripheral I/O pads to an area array of connections that are bumped at the wafer level.

Figure 2. A test chip from the Technical University of Berlin was redistributed from a peripheral pad pitch of 100 µm to an array area of 350-µm solder balls.
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It is still under discussion whether this is a real WLP or “just” a flip chip. IBM has been using area array designed ICs for flip chip assembly (the C4 process) for 30 years. It showed that having bumps on active silicon is not a limitation for this interconnection technology. Redistribution was used by IBM for rerouting ceramic multilayer substrates for flip chip attachment using thin-film technology. This redistribution technology based on low-cost thin-film process steps directly on the IC can even be used for ICs designed for wire bonding interconnection.

Redistribution became a big success. Fraunhofer IZM and the Technical University of Berlin started German and other European projects in 1995 to explore this technology for different applications (Figure 2).5-7 A number of German companies and two technical universities (TU Berlin and TU Dresden) formed a CSP consortium to deal with future requirements of chip scale packaging. More companies quickly came up with redistribution offered as a service in large volume for integrated passive devices, serial EEPROMs, analog and RF devices and power flash memory applications. The Flip Chip Division (FCD) of Kulicke & Soffa and Unitive created standards in this technology under the trade names UltraCSP (FCD) and Xtreme (Unitive). The thin-film polymer BCB from Dow (Cyclotene) became a popular dielectric material in WLP because of its low curing temperature and compatibility to copper.

The Second Wave: Additional Layers

The board-level reliability of WLPs based on a pure redistribution is limited by chip size, number of I/Os and distance to the neutral point if no underfill is used. Fraunhofer IZM and TUB started a program in 1996 to develop new concepts of high reliability wafer-level packages.8 A modified Mitsubishi package that could be manufactured completely at the wafer level showed promising results with FEM simulations based on a modified Manson-Coffin concept. Therefore, Fraunhofer IZM Berlin together with Motorola started to evaluate this concept of double solder balls and an additional stress buffer layer.9 The structure of this WLP is a pad redistributed die with a high lead solder ball array. A stress buffer layer embeds the high lead solder balls before second eutectic solder balls are placed on top of the embedded ball array. The basic idea is the deposition of an additional polymer layer on the redistribution layer to compensate the CTE mismatch of the die and the board by increasing the stand-off height. The result was a package that passed even 800 cycles (-55°C/+125°C) on board level for a 1 x 1 cm2 square die with a 14 x 14 ball array without underfilling. Motorola has successfully modified this approach using a photo-definable stress compensation layer to reduce the cost of the package.10

Table 1. A selection of new developments for high-reliability WLP.
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During the development of the double solder ball package, the Super CSP from Fujitsu was released.11 This technology is also based on a redistribution with a solder ball on a Cu post. The Cu posts are plated to a height of 100 µm on the area array pattern. A polymeric resin is molded between the studs. Preformed solder balls are placed on top of the studs. The wafer is then diced into single packages. A similar structure is used by IEP and Oki. The Super CSP is used for flash memory in the commercialized wrist camera from Casio. A variety of new developments have been initiated since then (Table 1).

The Third Wave: MEMS and MOEMS

A different technology approach was already released in 1995 by Shellcase.12 This CSP technology seals the wafer between two parallel glass plates. The peripheral pads are extended to the scribe line of the chip. The active side of the wafer is then glued to a plate of glass, and the wafer is thinned down to ~100 µm. A second glass plate is glued on the backside of the wafer and partially sawn to expose the extended pads. Runners are plated to an array area of UBM pads. Solder balls are attached and the final wafer is singulated by dicing. Shellcase tried to offer this technology for the packaging of memory chips, but it was more expensive than other WLP technologies. The change of the strategy from ShellBGA (with the active side of the chip flipped to the board) to the ShellOP package opened the way to MEMS and MOEMS packaging. There is access to the active side of the die in the ShellOP version. This technology appears, therefore, to be best-suited for optical applications.


In just a few years, wafer-level packaging has been shown to be a real alternative to other low-cost single chip packages for high-volume production. Therefore, WLP is not just an intermediate solution on the way to advanced flip chip but an improvement to flip chip technology using area array balls and stress compensation layers. All over the world, bumping subcontractors are including WLP manufacturing process into their production line. The success of this technology is reflected by the increasing numbers of new foundries and the strong WLP activity at IC companies. Further developments will include the extension of this approach to MEMS and even MOEMS packaging.


Michael Töpper, project manager, can be contacted at Fraunhofer IZM, Gustav Meyer Allee 25, D-13355 Berlin, Germany; 49-30-46403-603; Fax: 49-30-46403-623; E-mail: [email protected].


  1. M. Yasunaga et al, ,,Chip Scale Package: A Lightly Dressed LSI Chip,” IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings, La Jolla, California, 1994.
  2. S. Baba et al, “Molded CSP for High Pin Count,” Proceedings of the 4th ECTC, Orlando, Florida, 1996.
  3. J. Young, “The MSMT Package for Integrated Circiuts,” MicroSMT Application Notes, ChipScale Inc., 1994.
  4. R. Chanchani, K. Treece, P. Dressendorfer, “µBGA Technology,” International. Journal of Microcircuits and Electronic Packaging, 18(3) 1995.
  5. J. Simon et al, “A Comparison of FC Technology with CSP,” IEPS Proceedings, 1995.
  6. M. Töpper, J. Simon, H. Reichl “Redistribution Technology for CSP using Photo-BCB,” Future Fab International, 1996.
  7. M. Töpper et al, “Chip Size Package – The Option of Choice for Miniaturized Medical Devices,” IMAPS Conference Proceedings, San Diego, California,1998.
  8. J. Auersperg et al, “Reliability Evaluation of Chip Scale Packages by FEA and microDAC,” Symposium on Design and Reliability of Solder and Solder Interconnections Procedings, TMS Annual Meeting, Orlando,1997.
  9. M. Töpper et al, “Fab Integrated Packaging (FIP) A New Concept for High Reliable Wafer-Level Chip Size Packaging,” IEEE/ECTC Conference Proceedings, May 2000.
  10. B. Kether, E. Prack, T. Fang, “Evaluation of Commercially Available, Thick, Photosensitive Films as a Stress Compensation Layer fo Wafer Level Packaging,” IEEE ECTC Conference Proceedings, 2001.
  11. M. Hou, “SuperCSP: The Wafer Level Package,” SEMICON West Proceedings, San Jose, California, 1998.
  12. A. Badihi, E. Por: “ShellCase – A True Miniaturized Integrated Circuit Package,” Proceedings of International FC, BGA, Advanced Packaging Symposium, San Jose, California, 1995.




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