Hermeticity and cavity ambient control
BY ELS PARTON AND HARRIE TILMANS
Microelectromechanical systems (MEMS) contain fragile parts that require encapsulation in a hermetically sealed cavity for reasons of protection, reliability and tuning of performance. This can be realized using “zero-level” or wafer-level packaging techniques, whereby the cavity is fabricated during wafer processing. Recent research has focused on the development of packaging techniques offering good hermeticity of the cavity and controllability of the cavity ambient.
Packaging Requirements for MEMS
MEMS often contain moving parts. Hermetic encapsulation is, therefore, essential to protect these fragile parts against contamination from the atmosphere, dirt and moisture, as well as from mechanical and radiation loads. In this way, hermeticity of the cavity walls determines the reliability and the long-term drift characteristics of the device.
 Figure 1. The package cavity defined during (a) first-level packaging and (b) zero-level packaging based on chip stacking. |
Beside hermeticity, the controllability of the cavity ambient is a key characteristic to consider during packaging. In terms of device performance, it is important to define an ambient with a predetermined gas or gas mixture with a predetermined pressure. For instance, the time response of a microrelay strongly depends on the ambient pressure. Similarly, the thermal conductance of the ambient of a microbolometer must be as small as possible, implying the use of low-conductivity gases sealed at a low pressure.
Zero-level Packaging vs. First-level Packaging
First-level packaging consists of the chip capsule and the leads for interconnecting the chip to the outside world. Examples of first-level packages are ceramic, metal can or plastic molded packages. Cavity formation during first-level packaging is an established method that allows flexibility with respect to the composition of sealing gas and the sealing pressure (Figure 1a). Drawbacks of this approach are the high cost of ceramic and metal can packages, and the danger of exposing the fragile MEMS device to handling and contamination during wafer dicing and subsequent cleaning. Plastic packages, which are cheaper, are not suitable for housing “naked” MEMS devices because of the nature of the molding process.
The zero-level packaging or wafer-level packaging approach adds a packaging step carried out prior to the first-level packaging (Figure 1b). It offers many advantages compared to sealing during first-level packaging because the chances for damaging the fragile moving parts during wafer processing are minimized. Moreover, this approach allows the use of low-cost plastic packaging for final encapsulation.
The Indent Reflow Sealing Method
A zero-level package can be realized by two different approaches: surface micromachining techniques or wafer stacking based on wafer bonding. In the first approach for zero-level packaging, the cavity contains an access channel for the sacrificial layer etchant, which is closed after completion of the sacrificial layer etch. An advantage of this approach is the ability to seal a number of wafers simultaneously. On the other hand, this technique is characterized by limited control of the cavity atmosphere.
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Figure. 2. Process flow of the IRS method: (a) Deposition and patterning of under-bump-metallization (UBM), metal spacer and solder on chip #1, and of the top surface-metallization (TSM) on chip #2. This is followed by the creation of an indent in the solder and alignment of both chips on the flip-chip tool. (b) Pre-bonding of both chips on the flip-chip tool at an elevated temperature below the solder melting point. The self-sticking assembly is now ready for transfer to the reflow oven. (c) In a reflow oven after evacuation and, if required, filling of the cavity via the indent with desired gas or gas mixture at the desired pressure. (d) In a reflow oven after solder reflow, thereby closing the indent and sealing the cavity.
In the second approach, a stack of chips or wafers is built whereby the MEMS structure is capped with a chip. Different techniques exist for bonding the different chips: anodic bonding of glass to silicon, silicon direct bonding and bonding using intermediate layers (such as solder, low-temperature glass or a polymer adhesive). The process and materials employed determine the hermeticity and controllability of the cavity ambient.
A drawback for all of these methods is the fact that a trade-off has to be made between the desired ambient (gas composition and pressure), quality of the bond strength, hermeticity of the seal and process throughput.
 Figure 3. Microrelay assembly mounted in a ceramic side-brazed package. |
With the indent-reflow-sealing (IRS) method, sealed cavities can be realized at the wafer level without the drawbacks of the aforementioned approaches. It provides both hermeticity of the cavity seal and controllability of the cavity ambient, two features essential for packaging MEMS. The method is based on a two-chip approach whereby the chips are flip-chip assembled using a solder bond. An optional spacer layer (e.g., made of nickel) is implemented underneath the solder layer on the bottom chip to allow a better control of the cavity height. With this approach, the cavity is not etched into the wafer, but instead is defined by the sealing ring created by the spacer and a solder layer.
Other steps of the IRS process flow are the creation of an indent, pre-treatment in a fluorine-based plasma (e.g., using SF6) to enhance the solder bonding, pre-bonding without closing the indent, and closing of the indent during the solder reflow step in a designated oven (Figure 2). This process flow demonstrates one of the key elements of the IRS technique – decoupling of alignment and sealing.
To ensure a safe transfer from the flipchip alignment and bonding tool to the sealing chamber, after alignment, a pre-bonding force is applied on the tool at a slightly elevated temperature. This makes that the two chips “stick” and can easily be transferred to a dedicated seal and reflow oven. In the oven, solder reflow and sealing is performed at the desired pressure and gas. This makes the IRS technique flexible with respect to the choice of the sealing gas and the sealing pressure. The fact that the actual sealing takes place after the flipchip assembly results in a marked cost reduction, because no vacuum flip-chip aligner is needed. Also, many hermetic packages can undergo reflow simultaneously in the batch oven process.
Application to a Microrelay and Microbolometer
We can conclude that the IRS method is a cost-effective zero-level packaging technique that allows protection of vulnerable MEMS devices at an early stage of the packaging process, resulting in a high yield and performance. The combination of all these features makes the IRS hermetic packaging technique useful for both space and terrestrial applications. These applications include microrelays (Figure 3) and uncooled thermal IR bolometers. The IRS method will be illustrated in these two devices.
In case of the DC microrelay, the IRS technique has been developed for housing the electrical contacts. An optimized packaging technique is important because the package influences the microrelay characteristics, particularly the ON-resistance (RON) of the ohmic contacts. With this new zero-level packaging technique, a microrelay with two flip-chip assembled chips at the heart was developed (Figure 4). A eutectic bond between electroplated tin-lead solder and gold is used for the assembly. Fully integrated electromagnetically actu ated microrelays have been successfully fabricated, with the first-level packaging being either ceramic side-brazed or plastic molded packages. Testing of these structures has revealed low operating voltages and currents (2 V, 8 mA), low RON (0.4 Ω), very high OFF-resistance (ROFF) (1013 Ω), acceptable operating times (1 ms) and maximum switching frequency (>500 Hz). This demonstrates the great potential to use these devices in low-power applications.
 Figure 4. Example of the use of the IRS method for creating the cavity for a microrelay. |
Another example of a device where the packaging is critical to the performance and reliability is the microbolometer. A microbolometer is a micromachined detector in which absorbed infrared irradiation is detected as a temperature change by using a temperature sensitive resistor, for example. It requires operation in vacuum and the integration of expensive IR optics into a camera system. Therefore, the IRS on-chip hermetic encapsulation method is used based on eutectic solder bonding of two plated rims. One of the rims surrounds the bolometers and the other, with the same geometry, is situated on a separate top substrate. Both rims, on the bottom (device) substrate and on the top substrate, are electroplated with NiAu and SnPb, respectively. The two substrates are next assembled using the IRS method described above. This approach again offers many advantages, including early protection of the vulnerable bolometers because the zero-level packaging is applied directly after releasing the bolometers and the addition of anti-reflection features to the Ge top substrate. Zero-level packaging of resistive bolometers is an important tool for low-cost and high-yield bolometer array fabrication.
It can be said that the IRS method presents an attractive technique for the on-wafer encapsulation of MEMS devices, such as microrelays and bolometers but also microresonators, RF-MEMS switches and micro-accelerometers. One of the technical challenges includes the specification, controllability and characterization of the cavity ambient and the her meticity as required for the small cavity volumes. The next step is to bring the IRS technique from small-scale R&D processes to a fully qualified industrial process.
AP
Els Parton, scientific editor, and Harrie Tilmans, research and development project manager, can be reached at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; 32-16-281-261; Fax: 32-16-281-501; E-mail: [email protected] and [email protected].