May 23, 2002 – Santa Clara, CA – Advantest Corp. plans to develop a fast, accurate failure diagnostics solution for deep-sub-micron, high-speed SoC designs leveraging TetraMAX automatic test pattern generation (ATPG) technology from EDA tool provider Synopsys Inc.
Currently under development, Advantest’s SoC failure diagnostics tool will use data communication between the company’s T6000 series ATE system and Synopsys’ TetraMAX ATPG tool to streamline the process of detecting failures in complex chips. The tool is slated for formal introduction in September.
“SoC development is increasingly focused on reducing time to market, improving production margins, reducing design and manufacturing costs, and implementing a design-for-test methodology that reduces the overall cost of test,” said Nick Konidaris, president and CEO of Advantest America Inc. “We are working closely with Synopsys to develop an SoC failure diagnostics tool that optimizes and streamlines communication between our respective SoC-focused tools to help chipmakers attain these goals.”
Advantest’s SoC failure diagnostics tool will transfer data on the location of the failure from the T6000 series ATE system to TetraMAX, enabling TetraMAX to utilize its failure diagnostic feature to identify the failure node, pinpointing the problem, the company said. The diagnostic tool, with TetraMAX support, will be effective for scan-based design. By automating the failure diagnosis process, the user can reduce the turnaround time of analysis for both the design and production-test teams.
“To ensure an optimal flow between Advantest’s SoC failure diagnostics tool and TetraMAX, Advantest is an active member of Synopsys’ in-Sync program for EDA interoperability,” said Karen Bartleson, Synopsys’ director of quality and interoperability. “Customers will benefit from a smooth, interoperable flow between Advantest and Synopsys tools that can help reduce their time to market.”
In addition, Advantest has implemented these failure diagnostics methods on its e-beam test system. Linking fault localization information and design information will enable more precise and accurate failure area and defect factors to be specified, the company said.