By Debra Vogler
WaferNews Technical Editor
As semiconductor manufacturers race against the industry roadmap, failure analysts have had to keep up their end of the design cycle/product cycle equation so the bottom line enablers – yield enhancement and advanced process development – proceed efficiently.
Being able to remove very small amounts of material in a controlled fashion is key to discovering the true nature of a failure. Many in the field have been evaluating and using focused ion beam (FIB) as an adjunct, or even replacement for, mechanical sectioning techniques. FIB has been used for years to repair chips or do minor design changes, but, when used properly, it can accomplish cross-sectioning without causing damage or compromising the nature of the defect being investigated.
However, the growing use of low-k dielectrics adds to the failure analyst’s burden of preventing the destruction of failure evidence during the course of the investigation. The reduced modulus of elasticity and porosity of the new dielectric films prevents using the once tried-and-true manual sectioning in which oxide surfaces are polished until they’re smooth. Soft materials tend to smear, while the brittle ones tend to fracture during traditional failure analysis preparation.
In light of the new challenges, even FIB is limited in what it can handle. For example, the beam can interact with low-k dielectrics. And gate oxides, which can be 2nm or less in thickness in advanced CMOS technologies with 130nm gate lengths and below, are becoming more and more difficult to probe. Sub-0.25-micron features can’t be optically imaged using conventional tungsten wire contact probes. Furthermore, when FIB CVD tungsten deposition is used to form probing pads, the result can be the unwanted implantation of gallium into the top surface of porous, low-k dielectric films.
To combat these problems, failure analysts are exploring atomic force microscopy (AFM) to precisely position multiple probe tips within a small footprint and perform electrical measurements on features as small as 0.50nm. (1)
“AFM as an electrical characterization tool for contact and non-contact probing has begun to supplant conventional tungsten wire contact probing in CMOS SOI structures involving low-k dielectrics,” notes Terry Kane, senior engineer at IBM’s Microelectronics Division. “These devices, which use partially depleted device designs that produce floating body effects, are prone to charge build-up resulting in gate oxide damage/rupture as well as gallium implantation into the low-k dielectric films.”
The use of new materials isn’t the only reason for exploring novel failure analysis techniques. The transition by IC manufacturers to the far more valuable 300mm wafers is another major driver and companies are vying for an edge in analytical techniques just as much as in their product designs.
“It used to be that design engineers didn’t especially like to see failure analysts,” says Ed Cole, a distinguished member of the technical staff in the Failure Analysis Department at Sandia National Laboratories. “Now, considerable revenue is being generated by IP from failure analysis techniques and, more and more, the field is being viewed as giving a company a competitive advantage.”
[For example, IBM licensed its PICA (picosecond imaging circuit analysis) technique to Schlumberger. Sandia has licensed its CIVA, LIVA and TIVA/SEI technologies to companies, as well as its entire failure analysis suite to an IC manufacturer.]
The unceasing efforts to reduce time-to-market and time-to-volume have also taken a toll on the science of failure analysis. Steve Ferrier, president and CEO at SDG Analytic, describes failure analysis as an island of scientific method in a sea of business pressures. “It’s clear that the scientific approach, when used to do failure analysis, must be modified to increase the speed with which results are achieved,” states Ferrier.
Some of the techniques proposed by panelists at a recent International Symposium for Testing and Failure Analysis (ISTFA) session that tackled the speed challenge include using failure profiling to quickly identify a failure cause, avoiding the “throwing it over the wall” syndrome by getting failure analysts involved in the problem-solving effort from the beginning, and eliminating segments of analysis by omitting defect identification or characterization.
“Failure profiling can be used to quickly assemble initial results from a group of tests and compare them, like a fingerprint, to a historical database of past failures,” explains Ferrier. “If there’s a match, we can analyze narrowly to find a cause like the ones we’ve seen in the past.”
With all the rush to find short cuts, the emphasis on photographing defects may have to be reduced as well.
“If we can omit defect identification or characterization and still identify the cause of failure, we avoid a sizable amount of work intended to give a picture of a defect in a circuit and provide an analysis of its chemical composition,” continues Ferrier. “We would like to escape the over dependence on pictures of defects [e.g., SEM, EDS, TEM] because of the time required to find, photograph and characterize them.”
Will all the work by failure analysts pay off?
It’s difficult to come up with exact numbers, but Cole figures that if a modern IC fab is down due to an unresolved defect producing a failure, the direct costs can easily exceed $1 million/day, depending on the product.
“If there is a delay in getting a product to market before your competitor who has better failure analysis tools, then the loss in market share makes the impact critical to the profitability and survivability of the manufacturer,” notes Cole.
(1) Electrical Characterization of Circuits with Low-k Dielectric Films and Copper Interconnects,” T. Kane, P. McGinnis, B. Engel, IBM Advanced Semiconductor Technology Center, ISTFA 2001 Proceedings.