BGA, CSP and flip chip

When to use which process, and why


Click here to enlarge image

It has been understood for many years why flip chip devices need to be underfilled. Traditional large ball grid array (BGA) devices are only underfilled on rare occasions when the device will be used in critical applications, such as flight computers. There has been debate for a number of years on the need to underfill chip scale packages (CSPs). Most package manufacturers try to design their CSPs so they do not require underfill. However, in practice, an underfilled CSP has greater reliability than one that is not underfilled. Many manufacturers underfill CSPs when the parts are used in portable electronic applications that users often drop.

When product testing shows that a device needs to be underfilled, the next step is to determine the most appropriate underfill process. This article discusses the differences in flip chip, CSP and BGA device underfills and reviews when and where to use each process.

Package Type Definitions
The term BGA covers a wide range of package types. In this article, BGA refers to a 35-mm or larger device with 760-µm solder balls. The term CSP describes devices with 250-µm solder balls and an interposer layer between the die and solder balls. The overall package size of a CSP is typically no larger than 1.2 times the size of the silicon. Approximately 100 names are used by package manufacturers to describe various CSP designs, and many have “BGA” in their designation names. Flip chips are bare silicon devices that have solder bumps in the 75-µm range (Figure 1).

Underfill Requirements
Flip chips have very small solder bumps, typically 75-µm tall. Without underfill, all forces related to thermal expansion are transmitted through these solder connections. The coefficient of thermal expansion (CTE) of silicon is 4 ppm/°C, solder is around 21 ppm/°C and the PCB is

17 ppm/°C (Figure 2). Bumps located the maximum distance from the neutral point (DNP) are most susceptible to failure. Underfill distributes thermal expansion stress and hence improves reliability.

Raw resin or epoxy has a thermal expansion of approximately 70 ppm/°C, which is considered high for flip chip applications. The addition of filler particles like silica lowers the effective CTE. Underfill resins are typically loaded with filler particles around 70 percent by weight, which reduces the CTE to approximately 30 ppm/°C. Adding filler to the resin to control CTE increases the cost of the underfill fluid. Filler materials are a major cost factor in the price of an underfill material. Also, a higher loading factor of filler materials slows the fluid flow under the device, thus increasing the time for the underfill process. Many underfill alternatives are designed to increase throughput and reduce the cost of materials.

Figure 1. Typical BGA, flip chip and CSP structures.
Click here to enlarge image

CSPs typically have solder balls or bumps that are 250 µm tall. The formula in Figure 2 shows the effect of solder ball height on stress levels when no underfill is applied. Doubling the aspect ratio of the solder joint will halve the stress on the solder bumps. Most of the applications where CSPs are underfilled are typical portable electronic equipment that use a battery for power. By far, most failures of portable electronic equipment with CSPs are caused by sudden mechanical shock. Therefore, it is less important to have a low CTE value for the CSP underfill materials. Adhesion of the part to the board and redistribution of the stresses from mechanical shock are the goals with this type of assembly.

The underfill fluid that is typically used in CSP applications is either lightly filled or has no filler. The epoxy materials act as glue where the filler materials have no adhesion properties. Therefore, the bond between the parts is higher. With less or no filler, the fluid flows much faster and the CSP underfill process is done in a few seconds. With no filler materials in the epoxy, the adhesive has a lower modulus compared to flip chip underfills. A current technical challenge is deciding how much underfill epoxy is required for CSP devices. Most CSPs today are completely underfilled, but several companies have experimented with only putting dots of material in the corners of the device.

A CSP device often has an interposer layer between the die and the underfill. This allows some flexibility in the choice of material filler and the cleanliness of the resin. In applications where the resin is in contact with the die surface, the epoxies are specified to have less than 10 ppm chlorine and other extractable corrosive contaminates. When the CSP underfill is not in contact with the die, a relaxed specification of 40 ppm is appropriate so the resin material can be less refined.

Capillary Underfill
Used for both flip chip and CSP underfill, capillary underfill is probably the most familiar process for underfill. Modern dispensing equipment is highly flexible and can be quickly reconfigured for a change of products. This process is typically done one device at a time and is considered to pose throughput limitations.

This method relies on the capillary forces between the fluid and the package/board for the speed of flow. The soldermask or package substrate surface and the die passivation can either help speed the flow or impair it. If there is any flux residue from the previous solder reflow operation, it can impede the flow of the underfill. For very large die (25 mm square) with small gaps, such as microprocessors, it is not unusual for the die to receive three dispensing cycles of underfill. Two of the cycles dispense a bead of underfill next to the die for filling under the chip, and the third cycle puts down a seal. Because the fluid flow controls the speed of the underfill, flow-out time can be as long as 30 seconds, so the process for underfilling a large die can be more than a minute. However, the actual time spent dispensing at one die is often less than 0.5 second per dispense. With large flip chips, the process throughput can be improved by putting more parts into the work envelope, allowing the dispense process to be performed on other chips while the material is flowing underneath others.

Figure 2. Underfill distributes thermal expansion stresses among solder bumps, silicon die and the substrate. The formula shows the effect of solder ball height on stress levels when no underfill is applied.
Click here to enlarge image

CSPs are typically 7 to 12 mm square and have a large gap to be underfilled. Most of the time these only require a single pass underfill and the fluids are either lightly or not filled.

No-flow Underfill
No-flow underfill has been promoted to speed the underfill process and cut down on the number of ovens in the line. Essentially it uses a chemical process to accomplish several operations. At one point the no-flow material acts as a flux and, through the heat of the solder reflow process step, it is converted to an underfill resin. No-flow proponents have suggested that it could be either screen-printed or stamp-applied to the substrate, which is a faster process than dispensing. However, if the substrate already has a wet solder paste on the surface, it is difficult to use screen printing. Stamping requires individual pads for each die size and is not often practical. No-flow materials can be applied using standard dispensing systems.

Another method of applying no-flow materials is jet dispensing. It is fast and non-contact, but the shot size is limited and it is only appropriate for smaller die where less than 5 mm2 of fluid is required and there are small gaps (such as 75 microns). For larger shots of fluid a linear positive displacement pump is more appropriate.

The typical process for no-flow materials includes application of the fluid on the substrate and placement of the component through the fluid. Depending on the size of the component and the pad layout, it may be necessary to hold the part down in the fluid to prevent the part from floating on the top of the fluid. By holding the part, the fluid wets the part's edge and eliminates any floating or rebounding of the component. Once the component is placed on the substrate, it is sent through a reflow oven, and the wetting forces of the solder are used to pull all the bumps and pads into alignment. In capillary underfill, placement alignment can be off by 50 percent and still have the component pulled into alignment with the solder pads. No-flow processes require more accurate placement because the fluid is thickening as it goes through the oven.

No-flow materials have no filler particles to modify the CTE value of the resin, and a CTE of 70 ppm is typical. This would suggest that no-flow underfills are more suited to board-level applications, although no-flow underfills have not been used extensively in this application. They do appear to be gaining some acceptance for CSP underfill.

A process detail worth considering concerns moisture in the board. With capillary underfill that is applied after reflow, the moisture in the board has already been driven out. The boards being processed with no-flow underfill require a pre-bakeout to remove this moisture. Boards may also require a post-reflow bake to ensure that the fluid is fully cured and converted from a flux state.

Reworkable Underfill
Capillary underfill uses thermoset materials, so there is no simple rework of the parts. By definition, thermoset materials do not soften with heat, unlike thermoplastic materials. A number of board manufacturers' test boards before the underfill step to allow for rework of a tested board. When the assembled board costs several hundred dollars, rework becomes attractive at any labor rate. Several material suppliers now have reworkable underfills that decay or soften with heat. The process temperature to release the part can range from 110° to 220°C. The die is removed with tweezers and the board requires a mechanical brush and solvent clean up of the solder pads. Reworkable materials can be used with either flip chips or CSP. Reworkable underfill fluids can be applied by standard dispensing methods using capillary flow to pull the fluid under the part.

Corner Bonding of CSPs
Several companies have been experimenting with corner bonding of CSP devices rather than completely underfilling the components. There are variations on the process, from putting down four dots of fluid after the component is reflowed to the board, to placing dots at the four corners before component placement and curing during reflow. While this is a new area of investigation, early results indicate that corner bonding is less reliable than full underfill. This is a classic trade-off of lower cost of process for less reliability.

Other issues to consider include special packages – those without bumps in the corner – are required when corner bonding with dots prior to placement; how large a dot of epoxy is enough to provide adequate reliability; and the throughput of corner bonding. It actually takes longer to place four glue dots with a needle dispenser than it does to put a bead of underfill next to a die.

Molded Underfill
The semiconductor packaging industry has used transfer molding for many years. A well-understood process, transfer molding is fast and has a low cost per part, but the initial capital investment is relatively high. Many companies already have a significant amount of capital invested in molding equipment. Also, traditionally the molding epoxy powders are much less expensive than underfill fluid. Hence, it is desirable to use molding techniques for underfilling flip chip devices when manufacturing BGA and CSP devices, particularly when one device type is being made in large quantities.

In this application, a laminate board has many parts bonded to the board. The boards are in strips and are often 100-mm wide. A panel can be divided into several sections 100-mm long. Each section contains many chips depending on the size of the die. The panel is loaded into a molding machine and two molds (top and bottom) are brought into contact with the board and clamped around the edge of the panel sections to eliminate mold flash. The powdered epoxy materials are pre-heated and liquefied, and then forced into the mold cavity to produce a 100-mm square block of epoxy under and over the flip chip die. This block and the base PCB panel are diced into individual devices after ball attach.

While this has been shown to be technically feasible, it is necessary to over-mold at the same time as underfilling the parts. Over-molding over the back of a flip chip is necessary because it is difficult to get the top mold to seal off against the back. When a die is over-molded, the minimum thickness of the over-mold needs to be 0.5 to 1 mm. Otherwise, the die can break the epoxy when it expands with temperature. Unfortunately, the cost of the underfill molding material powder is heavily driven by the cost of the filler particles, which are much more expensive than those used in conventional molding compounds.

Wafer-applied Underfill
Significant work has taken place to develop wafer-applied underfills. The advantage of this approach is to remove liquid adhesive products during the assembly process on a surface mount line. During placement in the board assembly process flow, a heated chuck bonds the underfilled CSP to the board. Alternatively, the underfill flows during solder reflow and bonds to the board. However, using a heated chuck in the placement machine slows the operation down, especially if each placement requires heat-up and holding steps.

So far, wafer-applied CSPs have been limited to small devices with only 1 to 2 mm from the package neutral point to the outer solder bump. The wafer-applied underfills are typically not filled and so they only lend themselves at this time to small devices or portable board assembly products.

There has been significant innovation applied to remove liquid underfills from packaging and board assembly. The established dispensing approach that is perceived as slow has improved tremendously in the past few years. While there are no universal solutions in underfill technology, many of the new technologies have been developed to solve specific problems, but there are still advantages to using a technology with a longer history and broader infrastructure. AP

Steven J. Adamson, product manager, can be contacted at Asymtek, 2762 Loker Avenue West, Carlsbad, CA 92008; 760-930-7424; Fax: 760-930-7239; E-mail: [email protected].


Recommended Reading

Basic Underfill
Martin Bartholomew, An Engineer's Handbook of Encapsulation and Underfill Technology, Electrochemical Publications, ISBN 0 901150 38X.

Daniel Gamota and Cindy Melton, “Materials to Integrate the Solder Reflow and Underfill Encapsulation Processes for Flip Chip on Board Assembly,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Part C, 21(1), January 1998.

Reworkable Underfill
Lawrence Crane et al., “Development of Reworkable Underfills, Materials, Reliability and Processing,” IEEE Transactions on Components, Packaging and Manufacturing Technology, 22(2), June 1999.

Molded Underfill
Tara R. Miles et al., “Transfer Molding Encapsulation of Flip Chip Array Packages: Technical Developments in Material Design,” SEMICON West 2000 Proceedings, San Jose, Calif., 2000.

Wafer Applied
Philip Garrou, “Wafer Level Chip Scale Packaging (WL-CSP): An Overview,” IEEE Transactions on Advanced Packaging, 23(2) May 2000.


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.