Advantest Corp., Tokyo, Japan, has plans to establish the Semiconductor Test Consortium — an industry-wide collaboration aimed at solving the challenges of cost-effectively testing complex logic devices, such as SoCs.

This nonprofit consortium is expected to focus on supporting the development of the Semiconductor Test Open Architecture, a new framework created to enable open test solutions that offer true hardware and software interoperability, with technical and economic benefits.

Advantest is presently recruiting participants for the consortium from the ranks of IC manufacturers to enable the development of a highly scalable and flexible test platform with a lifetime of more than 10 years. Currently, Advantest has active participation from half of the world’s top 10 semiconductor companies involved in a working group committed to launching the consortium, Advantest said.

Advantest’s Semiconductor Test Consortium will be open to all companies throughout the semiconductor supply chain with a vested interest in the test sector. The consortium plans to focus on the following goals: driving the direction of the Semiconductor Test Open Architecture; publishing the architecture and providing training programs and workshops to ensure it is truly open; identifying requirements, developing solutions, and defining and managing validation procedures to ensure full vendor interoperability; and engaging in joint marketing and promotion activities to educate the industry about the platform architecture and ensure its successful implementation.

According to Toshio Maruyama, president and COO of Advantest, “The establishment of the Semiconductor Test Consortium comes at a highly opportune time. As the industry begins to recover from a very rough period, companies are starting to step up the ramp of advanced manufacturing operations — making it imperative to address the process flexibility and cost challenges that chipmakers face in providing highly reliable devices in the most cost- and time-efficient manner. Advantest believes a fully open test architecture, supported by vendors throughout the industry, is critical to helping IC makers achieve these objectives.”

The current plan is for the founding members to begin reviewing the draft architecture by next month, with the ultimate goal of publishing the architecture and releasing the complete developer’s kit — including software, hardware, documentation, and training — in 1H03.