die products

Standards provide key to progress


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The current appeal of applications using die products has its roots in the rush to implement advanced packaging for competitive advantage in small form factor, consumer markets. The promise of bare die as the ultimate low-cost solution has been delayed because, until recently, special test and burn-in costs have made it difficult to achieve price parity with packaged components.

The challenge to the customer today is not whether they can procure the devices with the quality and reliability metrics they need, but how to ensure that they receive the information necessary to judge the cost of ownership of the solution. Figure 1 shows the promise of die products.

Industry Trends
Several industry trends are now converging that will contribute to the success of low-cost, high-reliability assemblies using die products. Most important, quality and reliability of the pro cesses to fabricate integrated circuits (ICs) are improving. Figure 2 shows the accelerating rate of fab ramp-up to full production – and, in turn, represents great strides in yield management in the industry. Defect identification and elimination is critical to ensure profitability in today's fiercely competitive industry. IC fabricators are becoming increasingly adept at eliminating defects that cause yield loss, customer returns and infant mortality.

Figure 1. Compounded annual growth rate (CAGR) of different packaging formats. (Source: TechSearch International, IC Insights)
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Another trend in the industry is that IC suppliers are performing final test and reliability screens at the wafer level to reduce scrap costs in the back end of IC production. High-performance probe cards, high-voltage stress and low-voltage tests are being put into production at major IC fabricators worldwide. Ideally, final tests and screens are applied at the wafer level.

The trend to outsource test and assembly operations of IC processing also has pushed the acceptance of die products. Outsourcing models rely on contract electronics manufacturers (CEMs) for typical back-end processing. Today's large, international packaging houses are developing equipment and processes to implement the latest in bare die assembly, including system-in-package, stacked die modules and wafer-level chip scale packages (WLCSPs).

The Role of Standardization
As a result of these trends, the die products industry has matured so customers can obtain the devices they need with the quality and reliability needed to realize profits. The next hurdle is to simplify the procurement transaction.

Users of bare die require more information than users of packaged ICs to design, handle and assemble the die product correctly. To enable transactions between buyers and sellers, minimum requirements for transfer of the unique die-related information must be defined, stated simply, and be defensible with data. An international standard being developed focuses on the unique information that must be available for successful application of die products in electronic assembly.

Previous Die Standardization Efforts
Several prior standards have addressed different aspects of die for wirebond and flip chip devices.

JESD 49 Procurement Standard for Known Good Die (KGD): This standard was created to facilitate the procurement and use of high-reliability semiconductor microcircuits or discrete devices provided in bare die form.1 It provides requirements and guidance to bare die suppliers for as-delivered performance, quality and long-term reliability expected of this product type. It also reflects the special needs of KGD product customers in terms of design and application data. This standard is seen in the industry as primarily a guideline that gives users a checklist of issues to be addressed in the transaction. It was drafted by a joint MCC/SEMATECH task group of industry professionals and submitted to JEDEC for standardization. It was released as a standard in 1996.

Figure 2. Rate of fab ramp-up to full production. (Source: Rose Associates, IC Insights)
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J-STD-12 Implementation of Flip Chip and Chip Scale Technology: This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies.2 The areas discussed include design considerations, assembly processes, technology choices, and application and reliability data. Chip packaging variations include flip chip, HDI, microBGA, microSMT and SLICC. It also provides general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies. This document was developed by IPC, EIA, MCNC and SEMATECH in 1996. This document has been approved by the American National Standards Institute (ANSI).

J-STD-26 Semiconductor Design Standard for Flip Chip Applications: This standard addresses semiconductor flip chip design requirements.2 It provides information for using standard semiconductor substrates, materials, assembly and test methods with established fabrication, bumping, test and handling practices. Electrical, thermal and mechanical chip design parameters and methodologies are covered in the standard, as well as the reliability aspects associated with these conditions and processes. The standard was developed by IPC and EIA and released in August 1999. It has been approved by ANSI.

J-STD-28 Performance Standard for Construction of Flip Chip and Chip Scale Bumps: This standard establishes construction detail requirements for bumps and other terminal structures used for flip chip and chip scale devices.2 The specific standards for different terminations are appropriately matched to a particular interconnection process and include such diverse terminations as solder bumps, columns, non-melting stand-offs and conductive polymer deposits. The document articulates a set of designations and expectations for product performance for the manufacturer and the user of flip chip or chip scale devices. Recommendations are provided to implement the best commercial practices and evolving process improvements. The standard was developed by IPC and EIA and released in 1999. It has been approved by ANSI.

EDR-4703, Quality Assurance Guidelines for Bare Die Including KGD: This guideline was developed by EIAJ's Technical Standardization Committee on Semiconductor Devices and was published in 1999.3 This is a guideline more than a standard. It proposes four levels of KGD that depend on the test and inspection regime for a device. These include visual mechanical, electrical characteristics, early failure and long-term reliability. These parameters are used to specify three levels of quality and reliability for bare die assemblies.

ES 59008, Data Requirements for Semiconductor Die: This European standard was developed to provide both the seller and user with a list of data required for the implementation of a bare die solution.4 It provided multiple levels of compliance based on a supplier's willingness to disseminate the required data. The specification defined the data requirements for bare die products in the following areas: product identity and traceability; product date; die mechanical information; test, quality and reliability information; handling, storage and mounting information; and thermal data and electrical simulation data.

This standard is a 12-part document that includes guidelines and good practice for companies in the die business in Europe. It was developed in response to the need for a way of presenting information in a standard way for inclusion in a database. The data could then be downloaded into CAD design stations to facilitate the layout and simulation of MCMs and hybrid circuits. This standard's several parts were adopted by the European Committee for Electrotechnical Standardization (CENELEC) between 1999 and 2002.

Current International Standard Development
To take maximum advantage of semiconductor industry trends, communication between the user and the supplier of die products must be improved. An International Electrotechnical Commission (IEC) working group representing companies and organizations of die suppliers in the Europe, Japan and the U.S. began formal meetings in 2001, and it expects to complete a standard by the end of 2003. The standard, IEC 62258 (Semiconductor Die Products – Minimum Requirements for Procurement and Use), is being developed to provide definitions and requirements for handling, shipping and storage of bare die.5 This will require disclosure of quality and reliability metrics for bare semiconductor die, with or without connection structures, and minimally packaged semiconductor die.

The standard focuses on the unique information that must be available for successful application of die products in electronic assembly. As with the European standard ES59008, which is being used as the background for this standard, it will be produced in several parts. To date, two parts have been developed in draft form and are being circulated for comment to the national committees of the countries active in the IEC activities.

Although IEC62258 is based on the European standard (ES59008), it is being simplified to include requirements for procurement and use in only one part, rather than the multipart IS59008. Other parts may be added as needed for special applications or processes. To date, part one is in draft form and is being circulated for comment to the national committees of the counties active in the IEC activities. Part one covers the requirements for data of a general nature, including product identity, product data and die mechanical information. It includes specific requirements for the data that are needed to describe the geometrical properties of die, their physical properties and the means of connection necessary for their use in the development and manufacture of products.

Part one also specifies the minimum data requirements for test, quality, assembly and reliability of the die products. It details information to facilitate the description, production, supply, and use of die products, including wafers, singulated bare die, and die and wafers with attached connection structures or partially encapsulated die and wafers (WLCSPs).

Assembly Yield is the Key
With more traditionally packaged devices, the “package” has been used to partition the assembly space at the package leads. By standardizing the footprint of package styles, the assembler was not concerned with the myriad of details at the first level of assembly. Parameters, such as die geometry, die lead treatment and back side die contacts, were simply not relevant to the package assembly operation and not usually specified in the data sheet. These factors are critical to assemblers of applications using die products, though. To simplify the transaction between a user and supplier, this standard defines data required from the die supplier in order to assemble the device correctly.

A major emphasis in this standard is on performance measures. The standard requires that the die supplier provide an estimate of its outgoing quality level for the particular die type. The standard recognizes that final module yield is dependant upon a combination of factors, including the individual die device defect level, quantity of die in the module, substrate design, handling, storage and interconnection process.

The company making the end product can predefine the defect level by determining the defect level that will provide acceptable module yield. The IC supplier may then condition the device as needed to meet the user's specification, recognizing that die costs may be affected if the user requires ultra-high confidence and special tests to enable the estimation. The standard also requires that the die supplier provide the user its estimate of early life failure for the die device type and provide a description of the method used to produce the estimate.

Electronic Data Exchange
To reduce the time to market and improve communication, electronic component manufacturers, component suppliers and OEMs are developing a uniform set of common standards for data exchange. The objective of the CENELEC standard ES 59008 – to produce a standard format for electronic data exchange of die information – remains a critically important issue for increasing the use of die products. It is imperative that the die products community have a voice in whatever format becomes the industry standard to ensure that it includes a structure that allows necessary die product information to be inserted. AP


  1. This document is available from www.jedec.org.
  2. This document is available from www.ipc.org.
  3. This document is available from http://tsc.jeita.or.jp/eds/sdrsl.htm.
  4. This document is available from http://www.cenelec.org/BASIS/celis/free/project/SDF.
  5. A preliminary copy of the draft standard is available on the Die Products Consortium Web site (www.dieproduct.com).

Larry Gilg, managing director, can be contacted at Die Products Consortium, 3908 Avenue G, Austin, TX 78751; 512-452-0077; Fax: 512-452-5141; E-mail: [email protected]. Jim Wolbert, director of total quality, can be contacted at Chip Supply Inc., 7725 North Orange Blossom Trail, Orlando, FL 32810; 407-296-5658; Fax: 407-290-0164; E-mail: [email protected].


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