EMI filter packaging



Most consumer electronic products today, especially handheld devices, require protection from electromagnetic interference (EMI). To accomplish this, they need filtering devices that are small, inexpensive, and can reject radio frequency interference (RFI) and interference from high-frequency clocks and other signal harmonics. A major concern for all wireless devices is interference caused by very high frequencies of RF transmission. An EMI filter both suppresses unwanted emissions and improves immunity to the transmissions of other RF devices, typically noise at frequencies above 800 MHz and as high as 2.5 GHz. To accomplish these tasks, appropriate filters must be used. Chip scale packages (CSPs), because of their tiny form factor and associated low inductance, enable good filter performance by permitting this high-frequency rejection.

EMI Filters
EMI filters are low-pass filters, which means that they permit low-frequency signals (typically from 0 to 10 MHz) to enter the circuit, but reject high-frequency components (typically from 100 MHz to 3 GHz), which are considered undesirable noise. Frequencies allowed to pass through comprise the “pass band,” while those rejected make up the “stop band.” The separating zone between the pass band and the stop band contains the “cut-off frequency,” which is typically defined as the frequency at which the signal is attenuated to 3 dB below the pass band. The attenuation rate, or signal amplitude roll-off rate, is determined by the slope of the attenuation curve for frequencies above the cut-off frequency. As maximum rejection of these stop-band frequencies is desired, steeper slopes are generally preferred. Single-pole (single RC network) filters provide an amplitude roll-off rate of -20 dB per decade, while CRC pi-type filters exhibit a much steeper signal attenuation rate of -40 dB per decade. Figure 1 shows the configuration of these two filter types and their respective frequency response curves.

Standard Approaches
Discrete components, such as thick film resistors and capacitors, are the traditional elements used to build low-pass filters. Such solutions provide flexibility in terms of resistance and capacitance values and number of suppliers. Several vendors supply integrated passive filter devices, which implement resistors, capacitors, and semicon ductor diodes on a single silicon substrate, for filtration and electrostatic discharge (ESD) protection. For example, one product offers a six-channel CRC pi-type EMI filter with ESD protection to replace up to 30 discrete components (six resistors, 12 capacitors and 12 diodes).

Figure 1. Frequency response for RC and CRC filters.
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Traditionally, silicon die for integrated passive filter devices have been packaged in SOIC, QSOP or other surface mount packages. For a CSP, solder bumps are mounted directly onto the die to provide the interconnect to the printed circuit board (PCB). Lab measurements comparing frequency response show attenuation versus frequency on a logarithmic scale up to 3 GHz for both a discrete solution and a CSP filter (Figure 2).

As seen in Figure 2, the attenuation curve for the discrete solution shows a resonant frequency where the attenuation peaks around 300 MHz. Above that, the attenuation decreases and the filter is not effective. The CSP device, by contrast, demonstrates aggressive attenuation peaking around 1 GHz and slowly decreasing thereafter, resulting in an attenuation of at least -35 dB between 600 MHz and 3 GHz. Above 1 GHz, enlarging the filter's integrated capacitor has little effect on the performance; the device's behavior is mostly dominated by residual inductance at these frequencies.

Figure 2. Attenuation curves for discrete components vs. CSPs.
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Parasitic inductance on the order of 1 to 3 nH in series with the capacitor to ground is the dominant factor that can cause a discrete filter's poor performance. This inductance derives from the discrete thick film component, and from the PC board trace interconnects between the components themselves (or from the bond wire and package lead for packaged devices). Comparatively, CSP solder bumps exhibit a parasitic inductance of only around 50 pH, allowing the CSP solution to significantly outperform its discrete component counterpart.

Zener diodes on each side of the CSP filter provide ESD protection against contact discharges in excess of +8 kV, per the IEC 61000-4-2 international standard. CSP products also offer enhanced performance during ESD transients, in that they avoid further voltage increases caused by package lead and bond wire inductance. Such ESD protection is a requirement particularly for filters located at I/O connectors, where they must protect sensitive internal integrated circuits (ICs).

CSP Process
Various companies produce devices using CSP technology, but only a few combine thin film passives and semiconductor processes to integrate diodes and other active devices that benefit from the CSP technology.

The CSP fabrication process involves the following steps:

  1. Under-bump metallurgy (UBM) is applied to a completed wafer, on each I/O pad of each die. The UBM is composed of a single or dual passivation layer of benzocyclobutene (BCB) and a thin film conductor layer (Al/NiV/Cu alloy) applied by sputtering. The UBM provides the interface between the die pad metallization and the solder bumps.
  2. Solder balls are then dropped precisely onto all wafer pads simultaneously, using a “ball-drop” placement machine. Typically, the solder bumps consist of eutectic pre-formed solder spheres, with an alloy composition of 63% Sn and 37% Pb.
  3. Wafers then go through electrical probe test, to verify functionality and compliance with the specification.
  4. Finally, the wafer dicing operation singulates the finished chips. They are then typically assembled onto a tape-and-reel, like any surface mount package components, or put in a waffle pack.

Balls are arranged in a fully or partially populated array, or in one or more concentric peripheral rectangles. EMI filters are offered in standard CSP formats with pitches of 0.5 mm (for 0.3-mm diameter balls) and 0.65 mm (for 0.35-mm diameter balls). The choice between these two pitches is normally made by users based on their ability to handle the devices in automated assembly lines, or their preference as it pertains to board routing ease (Figure 3). Cellular phone manufacturers, for example, are using 0.5-mm pitch devices in high volume comfortably. As a benchmark relating pitch and pin count to device size, a CSP device with a 3 x 4 ball array and 0.5-mm pitch measures only 1.5 x 2.0 mm.

Figure 3. CSP on a printed circuit board.
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Package marking is applied to both the topside and the bump side of the device. On the top (non-bump) side, a dot is placed in the corner at the A1 location, directly opposite the A1 bump. The dot is thus visible when the device is mounted on a PCB, allowing proper orientation to be verified during board assembly. A mark is also placed on the solder bump side of the device, next to the A1 pin. Additional character marking is also possible to identify the part, depending on space availability.

The CSP's height, which includes the die substrate thickness (about 0.38 mm) and the bump thickness, is approximately 0.65 mm total. This dimension is less than the smallest surface mount leaded package thickness, which can exceed 1 mm.

Board Assembly
CSP devices are typically placed on 8- or 12-mm wide carrier tape, with the bump side facing the bottom of the tape cavity. Components are oriented on the tape with the A1 marking toward the sprocket holes and the largest axis of the component perpendicular to the tape length. (It is important that the tape cavity size matches the die length, width, and height precisely to prevent device rotation or flipping, which would cause rejects during pick and place operations.) A heat-activated cover tape seals the device in the pocket like any other surface mount package. The tape is then wound onto 7-inch reels, after which the reels are ready to be shipped.

During surface mount assembly, the CSP is picked from the tape and placed on a module board or PCB. The assembly is then reflowed as with normal surface mount technology. Specialized CSP assembly equipment is not normally required.

One critical aspect of CSP use is the part's thermal coefficient of expansion (TCE). Because silicon substrates typically have a much lower TCE than organic board materials, such as FR-4, the resulting thermal mismatch couples mechanical shear stress to the silicon/ball and ball/board interfaces during temperature variations, and causes fatigue during the product's life.

The shear stress between the soldered component and the board increases with distance of the bump from the center of the die. Thus, larger die can be subjected to greater stress at their outboard bumps. One way to relieve some of the stress on the bump interface is to use an underfill material, although some CSPs are designed to be used without underfill and operate across the full industrial temperature range from -40°C to 85°C, as well as to be stored (in-system or out) across a storage temperature range of -65°C to 150°C. The use of properly sized ductile solder balls provide the required flexibility and interconnect reliability without requiring underfill.

CSP devices are recognized as an attractive advancement for EMI filter applications because of their performance, component integration density, I/O density and overall device size. The CSP package format, in combination with thin film integrated passive technology, provides an ideal solution in high-frequency EMI filtering applications, as well as vital ESD protection. AP

Fabien Franc, staff applications engineer, can be contacted at California Micro Devices, 430 North McCarthy Blvd., Milpitas, CA 95035; 408-934-3163; Fax: 408-934-2926; E-mail: [email protected].


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