Flexible flip chip

Solutions for high-performance applications


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As the demand for flip chip packaging continues to grow to a projected 12 billion units in 2005, the need for flexible, high-performance packaging products becomes more crucial.1 The demands for improved signal I/O density, better electrical and thermal performance, and die size optimization have driven developments in organic flip chip packaging technologies. Although cera mic substrate technologies have provided solutions for signal I/O designs, the need for better electrical performance and lower cost solutions has spurred the use of organic technologies.

Next-generation flexible flip chip offers an area array approach that optimizes die size and increases signal I/O counts; such flexibility marks a improvement over conventional peripheral designs and ceramic packaging solutions. A 1,000-signal I/O device in a cera mic package can require 10 to 15 layers, depending on the chip design complexity. In organic packaging, the substrate design can be achieved in five layers for the same chip design.

Communications devices, in particular, are demanding greater signal density and performance, and the ability to deliver such features in a cost-effective manner is paramount. To do that, it is advantageous to provide flexible features in generic package design solutions, eliminating the need for customization and reducing the overall chip design cycle. Providing such solutions in flip chip translates to cost savings when I/O counts are high, and the economics of choosing flip chip are a direct function of I/O count.2

Recent advances in what might be called “flexible” flip chip technology address cost, signal density, performance and quick design turns. The impact of using generic package designs speaks for itself. With hundreds of designs in wirebond ball grid array (BGA) packages, 95 percent of those designs use generic solutions. In peripheral organic flip chip, 98 percent of designs use generic package solutions. When considering the average time to design and tool a custom package, several weeks of package design for BGA packages alone can be removed from the cycle. Another advantage to generic packaging is that it affords the chip designer a good deal of flexibility in signal I/O count, as well as die size range. If the chip design changes from its initial stage to tape out, the generic package can accommodate this without changing the package design. But changes in custom flip chip packages can alter the package and redistribution layer layout, which may require modifications to the chip design, potentially causing delays.

Area Array vs. Peripheral Design
Many traditional flip chip designs employ a peripheral approach in which signal I/Os are restricted to the periphery of the die. The initial justification for using peripheral designs in organic flip chip was to respond to the challenge created by the inability of organic substrates to effectively escape I/Os from deep in the center of the package. Today, there are better design methodologies, and substrate suppliers have developed more aggressive design rules, both of which allow for area array solutions. With ceramic, a designer can achieve area array designs by stacking several layers, but there can be drawbacks to this approach, including cost, electrical performance and interconnect reliability.

Figure 1. Flexible flip chips use an area array approach, which provides several benefits over standard peripheral designs. This illustrates signal I/O cells on top of bump locations
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Next-generation flexible flip chip uses an area array approach for signal I/O placement to optimize die size, enhance electrical performance and increase signal I/O counts (Figure 1). Such a design allows signal I/O placement anywhere on the die, giving designers the flexibility to realize up to 60 percent die size reduction or to increase signal I/O density up to 65 percent compared to peripheral signal I/O solutions. Thus, a flexible flip chip can offer packages with up to 2,597 lead counts (1,728 signal I/O). This makes flexible flip chip well suited for communications applications that require large bandwidth, high-speed, and highly reliable data interfaces.

Why Organic?
Since their introduction in the early 1990s, organic substrates for use in standard plastic and enhanced plastic BGA packages have revolutionized the semiconductor industry. Similar substrate materials work well in flexible flip chips. When compared to ceramic, organic substrate technology offers high design density with respect to lines/spacing and via diameters (laser drilled or photo-defined), resulting in greater routing/signal density, fewer layers for escape and overall improved electrical performance. With the use of an organic substrate, the coefficients of thermal expansion (CTE) between the package and the printed circuit board (PCB) are closely matched, thus enhancing solder ball interconnect reliability (Table 1). This becomes particularly important when the body size of the package increases beyond 32.5 mm per side.

Figure 2. Relative simultaneous switching output (SSO) noise decreases significantly when using multi-layer organic flip chips.
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In addition to a decreased need for additional layers with organic substrates, thinner layers provide enhanced electrical performance in the form of reduced cross-talk and propagation delay (Figure 2). Organic substrates for flexible flip chip packaging technology have relatively low dielectric constants (2 to 4) compared to other substrate technologies, thus providing better electrical performance. Another benefit of organic flip chip is the developing infrastructure for material supply and assembly/test capabilities. During the past few years, the infrastructure to support high-volume assembly and test of organic flip chip has been adopted by most companies that offer subcontractor services.

Designing a Flexible Flip Chip
To support generic package solutions in flip chip, a standard bump pattern is designed, allowing any ASIC/SoC designer to use all of the standard package designs. To support all integration possibilities in SoC design, the generic package must be able to accommodate key attributes, such as:

  • Multiple Vdd I/O splits,
  • Controlled signal I/O impedance,
  • Separate core and I/O Vdd,
  • 100-percent differential pairs or single-ended I/Os, enabling support for high-speed differential signaling,
  • Direct die attach to a copper heat spreader, resulting in excellent thermal performance,
  • Matched CTE of package substrate to PCB, resulting in high solder joint reliability,
  • Flexible signal I/O placement anywhere on the die, and
  • Efficient escape routing from the package to the PCB.

Table 1. Comparison of substrate material properties.
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Flexible flip chip uses a package construction that was recently introduced, and it enables good thermal performance because the backside of the flipped die is attached directly to the copper heat spreader, covering the entire area of the package (Figure 3). Heat sinks can be added to the planar surface for additional heat dissipation.

Figure 3. The construction of the flexible flip chip is the same as other organic BGA designs, making it optimal for high-volume assembly.
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A common concern among users of area array packaging involves the efficient escape of signal I/Os from deep in the center of the package to the outer edge. Depending upon the number of I/Os to escape, PCB designers may have to design escape patterns that jog around other peripheral components (integrated circuits and passives). This can ultimately result in a PCB that is complex both in technology and in the number of layers used. The need for high-density interconnect design rules comes into play with many large-body area array solutions. To simplify this, the solder ball layout can allow for efficient escape routing from package I/Os to the PCB while also taking into account the need for signal integrity. Maximizing routing efficiencies results in reduced design time, enhanced electrical performance, relaxed PCB design rules, and lower overall cost and risk. Other benefits of such a design include controlled impedance I/O traces (50 Ω single-ended, 100 Ω differential), reduced cross-talk, improved signal propagation delay and a low thermal impedance path from the chip to the ambient.

A generic line of flip chips with standard construction lends itself to high-volume assembly, where economies of scale make such solutions affordable for product manufacturers and, ultimately, end users. Flexible flip chip is well- suited for high-speed, high-performance applications in communications and storage products, including Internet switches and routers, optical routers, wireless basestations, computer servers and workstations, and storage systems.

Future Challenges and Ongoing Research
With the use of flip chip projected to grow at a rate of 20 percent annually through 2005, the need for enhanced flip chip packages will continue to drive research and development.3 Applications for the future will need higher frequencies and increased bandwidth, and support of optical networking systems using OC-192 and OC-768 protocols requires packages that do not inhibit the performance of chip designs. As silicon processes continue to follow Moore's Law at the 90 nm technology node and beyond, packaging will be required to match chip design performance, die sizing and increasing signal I/O counts into the thousands. The future will also require further enhancements in thermal performance. AP


  1. Prismark Partners LLC, “Array Packages Revisited,” Feb. 2001, p. 1.
  2. Shankara Prasad, “Technology Comparisons and the Economics of Flip Chip Packaging,” Advanced Packaging/Solid State Technology Supplement: The Next Step, March 2001, pp. 18-24.
  3. Electronic Trend Publications, “Advanced IC Packaging Markets and Trends,” 5th edition, January 2002.

Stan Mihelcic, manager, advanced packaging solutions, can be contacted at LSI Logic, 1551 McCarthy Blvd., Milpitas, CA 95035; 408-433-7426; Fax: 408-433-7241; E-mail: [email protected]



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