Lithography for Advanced Packaging

Process issues and solutions

Click here to enlarge image


With the evolution in front-end semiconductor technology and end product platforms, there is a need for further process development to package these products effectively. Foremost among these growing advanced packaging techniques is the use of flip chip and wafer-level chip scale packaging (WLCSP). Because of the complex nature of these packaging techniques, the transition to wafer bumping and chip scale packaging has resulted in the migration of front-end manufacturing techniques into the traditional back-end manufacturing arena. The rapid increase in chip density and input/output (I/O) requirements, as well as the implementation of multilayer I/O redistribution, has resulted in the implementation of lithography for packaging processes. These requirements have resulted in the proliferation of 1X stepper lithography as a suitable method of image transfer for wafer bumping and WLCSP.

Flip Chip Technology
Widespread adoption of flip chip technology has been driven by increased integrated circuit (IC) performance and form factor advantages. Recent underfill material developments have ensured successful transition to eutectic Sn/Pb solder bump technology. The four main solder bumping techniques are evaporated solder bump, electroplated solder bump, screen printing and stud bumping.

Historically, both high- and low-pincount devices have used flip chip technology. The use of flip chip becomes mandatory on any die whose I/O count is so high that the pads cannot fit around the die perimeter or where the speed of signal propagation within the device is compromised by the use of wire bond technology. Flip chip also has found a niche within the low I/O devices. The ability to move the bond pads beneath the die allows for a smaller footprint.

Figure 1. Flip chip market growth by application (2001-2005). (Source: TechSearch International)
Click here to enlarge image

The potential expansion of flip chip technology into the mid-range pincounts represents a shift in the adoption of the technology, as well as a maturing of the industry. Figure 1 shows the flip chip market by application.

Figure 2 shows the significant growth rate expected in the solder bump market through 2005.1

WLCSPs are a unique form of CSP, where the die is not singulated from the wafer before packaging. The trend for miniaturization of devices has pushed toward the adoption of WLCSP. Theoretically, WLCSP should be a low-cost packaging option because processes are performed in parallel rather than sequentially on individual chips. A developing infrastructure and the adoption of these devices for volume mass production eventually will make the low-cost option a reality.

Figure 2. Wafer bumping growth (2000-2005) for flip chip in package (FCIP) and flip chip on board (FCOB). (Source: TechSearch International)
Click here to enlarge image

Figure 3 shows the growth of WLCSPs. With advances in process maturity and cost reduction, WLCSP will invade the DRAM sector.2 WLCSP use in DRAM applications will lead to the adoption of this technology in mainstream volume production.

Figure 3. WLCSP growth (2001-2005).
(Source: TechSearch International)
Click here to enlarge image

It is very challenging to predict the split between WLCSP and flip chip over the next five-year period. Part of this difficulty results from the subtle and evolving characteristics that differentiate the two packaging technologies. One differentiation is the pitch and the solder ball size. Typically, WLP involves 0.5 mm or greater pitches of area-array connections with solder ball dimensions of 150 µm or more. Flip chip applications involve either peripheral or area array I/O, with pitches of 0.25 mm or less, with solder ball dimensions less than 125 µm. Additionally, flip chip devices typically require underfill material while CSPs are expected to provide sufficient board-level reliability without the addition of any underfill material.3

300-mm Wafer Bumping
There are various factors promoting the adoption of flip chip and WLCSP processes on 300-mm wafers. The most important factor is the type of devices typically being fabricated on 300-mm wafers. It is expected that 50 to 65 percent of the devices fabricated on 300-mm wafers will require some form of bumping. Figure 4 shows the growth for 300-mm wafer bumping as a function of merchant and captive bumping.

Advanced Packaging Lithography Challenges
Semiconductor manufacturers have moved away from the use of contact and proximity aligners for front-end applications because of yield and imaging performance concerns. As flip chip and WLP techniques achieve industry acceptance, device manufacturers are faced with several manufacturing challenges. To address the technology needs, they are applying traditional front-end lithography equipment to leading edge back-end packaging applications. This adoption also has been accelerated by the realization that imaging requirements of wafer bumping are subject to the same production necessities as front-end semiconductor fabrication.4

Imaging Performance: Projection optics can offer good imaging performance. The resolution and image quality obtained using a contact or proximity aligner is a function of the gap between the wafer and the photomask. The best image quality is obtained when the wafer and the photomask are in direct contact, and it is reduced as the gap between the photomask and wafer widens. This leads to several issues with respect to imaging performance and yield. However, with stepper technology, the resolution and image quality obtained are a function of the wavelength of the exposure light and the numerical aperture of the system and not the proximity of the photomask to the wafer. Additionally, because 1X steppers produce a “projected” image, the ability to focus this image at various depths within a thick resist film enables good sidewall angles and overall image performance regardless of the resist film in use. This is especially critical in the advanced packaging market where the use of thick resist films is quite common. On the other hand, contact and proximity aligners have virtually no focus capabilities and, thus, have poorer performance for these types of films.

Figure 4. 300-mm wafer bumping growth (2001-2004).
(Source: TechSearch International and internal estimates)
Click here to enlarge image

Contact and proximity aligners also have difficulty maintaining exposure uniformity over large wafer sizes because of their requirement of illuminating the entire wafer for each exposure. Steppers illuminate a much smaller area for each step and, therefore, are able to control the illumination uniformity better. This results in improved CD uniformity and more consistent resist side wall profiles.5 Improved CD performance and more consistent resist side wall profiles lead to more accurate bump heights, thereby increasing the overall product yield.

Alignment Performance: The use of enhanced global alignment techniques during exposure while using stepper technology also can provide significantly better alignment capability. Because the image is stepped over the surface of the wafer, a 1X stepper can compensate for mask run out, isotropic wafer scaling, rotation errors and orthogonality errors by adjusting the exposure locations on the wafer during the alignment step. Contact and proximity aligners can conduct alignment only on a global basis because of the full array photomask requirement. Alignment for a contact or proximity aligner is accomplished using only two alignment targets and cannot compensate for mask run out or grid errors. Unlike the quartz reticles used for imaging with stepper technology, contact aligners use sodalime photomasks. The coefficient of thermal expansion (CTE) mismatch between the sodalime photomasks and the silicon wafers, coupled with the long exposure times required while exposing using contact or proximity aligners, results in significantly degraded alignment performance.

1X systems also can enhance overlay performance through the use of machine vision alignment system (MVS). This alignment system uses pattern recognition to align the reticle to the wafer. This method of image capture ensures that no special alignment targets are required on the wafer. This alignment has shown to be robust with alignment through thick films and low-contrast images.5

Process Yield: One of the most important factors in lithography tool selection is the ability to print defect-free images on a wafer, thereby eliminating the lithography tool as a yield detractor.

The implementation of stepper technology also eliminates the incidental wafer to photomask contact witnessed during imaging using contact aligners. This contact reduces the life of the photomask and introduces residual resist on the photomask, which leads to repeating damages during imaging. The use of enhanced global alignment also contributes to significantly better process yields by reducing the alignment errors and improving the quality of the image being exposed. The high level of process automation provided by stepper technology typically reduces operator intervention and can provide a more robust process.

Challenges for 300-mm Wafer Bumping: All these concerns related to imaging wafers are even more apparent when bumping 300-mm wafers. In addition to the imaging, alignment and yield concerns, the use of contact or proximity aligners necessitates the use of 14″ masks during lithography. According to industry sources, mask-related defects are a major source of contamination during the wafer bumping process.6 The 14″ masks used by contact/proximity aligners can result in a significantly higher defect level than the 5 or 6″ reticles used in 1X steppers.

It is expected that some 300-mm wafer bumping production lines will be foundries handling wafers from various sources. The ability to handle multiple wafer sizes and thicknesses during the lithography process sequence will provide a significant advantage for these foundries. The inherent design of a contact or proximity aligner limits their flexibility and makes this change difficult, time consuming and more cumbersome. 1X steppers have been able to automate this operation and provide a flexible lithography tool for the end user. AP


  1. J. Vardaman et al., “The Market for Wafer Bumping,” a commissioned study, October 2000.
  2. T. DiStefano, “Wafer Level Establishes a Beachhead,” Chip Scale Review, November/December 2001, p. 11.
  3. T. Tessier et al., “Technologies and Trends in Wafer Level Packaging,” Future Fab International, Issue 11, July 2001, pp. 363-369.
  4. S. Kay et al. “Analyzing Issues for 300-mm Back-end Lithography,” Solid State Technology, July 2001, pp. 138-142.
  5. M. Ranjan et al., “Edge Processing Solutions for Advanced Packaging Lithography,” Advanced Packaging, December 2001, pp. 35-38.
  6. B. Adams “Inspecting Bumped Wafers,” Semiconductor International, October 2000.

Manish Ranjan, senior product marketing manager, and Stephen Kay, director of product marketing for packaging technology, can be contacted at Ultratech Stepper Inc., 3050 Zanker Road, San Jose, CA 95134; (408) 321-8835; Fax: (408) 325-6444; E-mail: [email protected] and [email protected].



Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.