Motorola, Philips, ST introduce 90nm CMOS design platform

Aug. 27, 2002 – Austin, TX, Eindhoven, Netherlands, and Geneva, Switzerland – Motorola, Philips, and STMicroelectronics have unveiled a 90nm CMOS design platform that allows designers to start next generation SoC product development for low-power, wireless, networking, consumer, and high-speed applications.

The new 90nm CMOS design platform, available from all three companies, takes advantage of the multiple features and modularity of 90nm process technology. In particular, multiple threshold-based library elements can be selected at the design level and used in the same design block, providing users of the platform greater flexibility to optimize performance and power consumption, the companies said.

“This design environment brings to the market the combined strengths and experience of the Motorola/Philips/ST alliance,” said Chris Belden, corp. VP and GM of technology & manufacturing for Motorola’s semiconductor products sector. “Tremendous intellectual resources are being applied to this partnership.”

The full library platform includes:
*Two standard cells libraries, optimized respectively for performance and density, offering a selection of more than 1,000 cells; densities of more than 400Kgates per mm2 and supporting a core supply of 1.0V or 1.2V, with metal pitches of 0.28-micron and from six to nine metal routing layers; each library is offered with multiple Vt variants;
*Full range of 1.8V, 2.5V and 3.3V I/O cells;
*Extremely dense embedded memories, including 6T-SRAM enabling density from 1.6 to 1.2mm2/Mbit, dual port, register files and ROM compilers;
*A fully compatible low-cost process variant, allowing up to 32-Mbit of embedded DRAM with a density of 0.5mm2/Mbit.
*Further extensions to the initial offering, including SOI versions and high-performance integrated passive devices will be available soon.

A shuttle multi-project reticle service is already available with short cycle times, providing significantly reduced NRE charges for small wafer volumes and therefore enabling low-cost prototyping, the companies said.


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