Packaging of Cu/low-k Addressed at IITC

BURLINGAME, CALIF. – The annual International Interconnect Technology Conference (IITC) added advanced packaging as one of its focus topics this year. The bulk of the conference covers wafer processing associated with copper deposition, dielectric materials, planarization and other topics related to the creation of interconnect on the top of wafers, but packaging has emerged as an important part of an integrated device interconnect scheme.

A critical topic in interconnect recently has been the packaging of devices containing the low-k dielectric materials that are appearing in the current generation of silicon devices.

A team from International Sematech, Motorola, Infineon, Kulicke & Soffa Flip Chip Div. (FCD), and Philips had a paper titled “Packaging Assessment of Porous Ultra Low-k Materials” that investigated the performance of different assembly technologies and integration schemes. They demonstrated that the standard FCD flip chip process, gold ball bonding and aluminum wedge bonding can be used successfully if the wafer process is improved. Changes to the process included a more mechanically robust stack of layers in the interconnect structure, thicker passivation and an additional oxide layer.

The authors noted that a thorough assembly test is needed to evaluate low-k materials because the wafer fab yield with the successful integration scheme was similar to the yield of schemes that later failed during wire bonding or flip chip processing. In short, there is not yet a good pre-assembly indicator of the suitability of chip interconnect structures for packaging processes.


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