Sept. 9, 2002 – San Jose, CA – EGsoft, a division of Electroglas Inc., a supplier of process management tools for the semiconductor industry, has developed a software solution that will expedite semiconductor manufacturers’ ability to locate the physical origins of electrical faults in random-logic IC designs, in partnership with International SEMATECH (ISMT), Intel, and Texas A&M U.
The ultimate goal of the project, which was funded by ISMT, the international consortium of semiconductor manufacturers, was to enable chipmakers to significantly reduce time-to-market for new product designs and improve yields.
The results of initial testing and certification performed by Intel in its Santa Clara, CA, facility, showed a reduction in the time required to identify the physical cause of electrical failures.
“This project is essentially bringing the ability to efficiently find the root cause of failures in the non-memory area of the chip to enhance our manufacturing efficiency,” said Kambiz Komeyli, simulation and failure analysis group leader at Intel. “From our experience these developments easily integrate with the products and processes semiconductor companies are currently using for failure characterization.”
According to Fred Lakhani, the project manager and senior member of technical staff for the yield management group at ISMT, “Fault to defect mapping on logic products has been considered a significant need by the International SEMATECH member companies for some time now. The fault localization research conducted by professor Hank Walker of Texas A&M U. along with EGsoft’s emphasis on fault to defect mapping capabilities, were combined to develop a solution that addresses those needs. The functionality of this solution has been tested for feasibility at Texas Instruments and more recently beta tested at Intel.”