IBM looks to nano self-assembly
for semiconductor industry future

LAKE GEORGE, N.Y., Sept. 12, 2002 — Nanotechnology and nanomaterials will be critical to solving the semiconductor industry’s formidable challenges, said John Kelly, IBM senior vice president and a keynote speaker at the Albany Symposium on Global Nanotechnology, which began Wednesday.

One sign of nanotech’s rising role in the chip-making business was obvious in the event’s new name. Last year’s meeting was called the Albany Symposium on Global Semiconductor Issues.

At that 2001 gathering, New York Gov. George Pataki and industry leaders began talks that lead to the creation of SEMATECH North, a new branch of the industry consortium now headquartered in Albany Nanotech in the University at Albany. SEMATECH North will focus on developing nanotechnologies for advanced chip-making processes.

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This year’s symposium comes during a busy week in the small tech industry, as a number of other conferences are going on across the country, including the 2002 International Commercialization of Micro and Nanosystems Conference (COMS) in Ypsilanti, Mich.

In welcoming the audience of 250 to Albany, most from the business sector, Robert Helms, International SEMATECH chief executive officer, encouraged attendees to spawn another cross-industry collaboration to match the $400 million SEMATECH North project.

IBM’s Kelly keynote address focused on the great challenges the semiconductor industry will have to surmount to continue growing.

He noted that as chip components continue to shrink toward the nanoscale and silicon devices become more complex, creating the “masks” or templates used to etch them via photolithography will become prohibitively expensive.

Such masks currently cost upwards of a million dollars per set, Kelly said, and will become much more costly as the industry moves toward the shorter wavelengths and dimensions of extreme ultraviolet, or soft X-ray, lithography.

Kelly said IBM is looking toward a “maskless” future in which circuitry patterns as small as 10 nanometers are made not with light rays, but through molecular self-assembly. “We’re relying on nanotechnology to create materials that will self-select to produce features at the critical dimensions our technology needs to move forward,” he said.

While photolithography will not hit the wall in the near future, Kelly surveyed three techniques that IBM researchers were investigating to create nanoscale patterns on a wafer surface without photolithography.

One approach entailed embossing a nanotextured pattern on silicon that could serve as a kind of pegboard for attaching components. Another used a polymer layer to create a crystalline template on the chip surface. In a third approach, an array of 50-nanometer silicon pillars could serve as attachment points for 10 nanometer capacitors or other components.

Kelly also said he thought carbon nanotubes would find their way into semiconductor devices sooner rather than later. “When I was here last year, I said that carbon nanotubes were 10 to 20 years off,” he said. “The progress the world has made in only a year has really surprised me.”

He cited research at IBM and elsewhere that has advanced from producing single nanotube transistors to building working circuits in less than a year.

Nanotubes could also be essential for solving the problem of current leakage that traditional transistors encounter at the nanoscale, Kelly said. “Last year nanotubes were interesting, far-off research. Now I think we’re going to see increased activity around nanotube devices because of their performance and density characteristics, but also because they get around the current leakage issues.”

Even the copper wires that interconnect different parts of a chip are running into new challenges as they get smaller. “Surface roughness, grain structure and impurities can affect how well they conduct,” he said. Insulating copper wires from silicon is also becoming a much larger challenge as chip dimensions shrink.

“As we move from 130 to 90 to 65 nanometer (architectures), we’ll have to throw more and more nanomaterial capabilities at these issue if we want to solve these very difficult problems,” Kelly said.

It’s all in the packaging

Meanwhile, at COMS 2002 in Michigan, packaging was on many minds. Packaging can be an afterthought to entrepreneurs and investors — a funny stance, experts say, considering it can be one of the most costly and time-consuming parts of small tech production.

Speakers on a panel Wednesday devoted to the topic of packaging included Robert Mehalso, an industry consultant and founder of Microtec Associates. He said management and venture capitalists often don’t appreciate the challenges of packaging and seldom budget for its development — even though it can represent up to 80 percent of production costs.

Henning Wicht of Wicht Technologie Consulting in Germany said another challenge comes in the sheer number of approaches. “There are as many packaging solutions as applications” for microsystems, he said, because of the sheer diversity of shapes, sizes, strengths and functions of the devices.

He said the best solutions are those that combine packaging and housing into one system. Techniques like wafer-level packaging can reduce costs by 50 percent while boosting integration of parts.

Wicht encouraged developers to consider all options — and not get too attached to one approach.

“Many (packaging) technologies are complementary, not competing,” he said. “A combination of technologies allows you to meet the target price.”

Mehalso recommended lobbying governments to invest in commercial packaging incubators and innovation centers for micro and nanotechnologies. He said such centers, including one proposed in the United Kingdom, eliminate the need for customers to pay for capital equipment and reduce the time to market.

(Small Times Staff Writer Jeff Karoub in Ypsilanti, Mich., also contributed to this report.)


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