Nanosize chips are not nanotech,
but the industry benefits, anyway

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Sept. 25, 2002 — It’s beginning to look a lot like nano in the computer chip industry. But while experts say chip features below 100 nanometers is not necessarily nanotechnology, the small tech industry may still benefit from breakthroughs made by its silicon cousins.

In 2003, Intel Corp. will begin etching its next generation of computer chips onto wafers of “strained” silicon, a form of the familiar material that allows electrons to move more freely. The new chips will feature 90-nanometer transistors, with gate insulators a mere five atoms thick. By comparison, current Pentium 4 transistors are 130 nanometers.

A new partnership between Motorola Inc., STMicrolectronics and Philips will also start making 90-nanometer chips by the end of 2002.

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But to be small tech, say industry experts, it’s not enough just to be small. Industry consensus says that true small tech is not just technology on the micron- or nanoscale; it also senses, sorts, reacts or responds to its environment, or involves human manipulation of material on the nanoscale to produce desired properties. However, while mainstream chip-making’s moves into the sub-100-nanometer realm can be better defined as miniaturization, small tech may gain indirectly from the research, experts say.

Like many technological innovations, strained silicon isn’t totally new. AmberWave Systems Corp. of Salem, N.H., and IBM have been working with it since AmberWave founder Eugene Fitzgerald pioneered the material at MIT and Bell Labs in the early 1990s.

David Welch, chairman of the materials science department at Brookhaven National Laboratory, said that AmberWave’s and IBM’s ability to form such small, well-controlled structures is significant. Being able to do it in commercial volumes is even more important. “This detailed understanding of how to create materials with such precision could certainly have wider value” in developing other materials with desired nanoscale properties.

Jim Yardley, managing director of Columbia University’s nanocenter, noted that AmberWave’s success in solving strained silicon’s technical challenges represents “a triumph in materials science.” While strained silicon may be the fruit of traditional materials science and physics, it has many qualities of a nano-engineered material — namely, precise control of the structure and characteristics of atoms.

While IBM and AmberWave have different processes, strained silicon is typically produced by first depositing silicon germanium onto a substrate in a carefully controlled gradient. Because silicon germanium’s crystal structure is larger than silicon’s, when a surface layer of silicon is grown on top of it, the silicon is atomically stretched apart by the underlying material.

The resulting molecular tension enables electrons to flow more readily, but can also cause defects that inhibit electrons.

Paul Welser, manager of IBM’s strained silicon program, said that until now the technology wasn’t a commercial imperative because other technologies and techniques kept improving chip performance for nearly a decade. With silicon transistors beginning to reach their practical size limitations, he said IBM is moving to produce all of its PowerPC and server microprocessors with strained silicon in about two years.

IBM will integrate strained silicon with the silicon-on-insulator (SOI) technology it pioneered in 1997 to build a new generation of chips with a 65-nanometer transistor architecture.

Welser noted that moving to strained silicon may spur demand for related small technologies, such as Raman spectroscopy for measuring strain in surface layers.

According to Tim Harper, chief executive of CMP Cientifica and executive director of the European Nanobusiness Association, strained silicon may also offer an alternative to expensive materials with high electron mobility such as gallium arsenide and indium phosphide used in high-speed and wireless components.

But Harper, co-author of the Nanotechnology Opportunity Report and a former engineer at the European Space Agency, said that strained silicon is “physics rather than nanotechnology.” But, he added, “once you start combining faster, lower-noise technologies with denser integration, you can produce faster devices at a lower cost. I suppose the impact on the semiconductor industry will feed through into small tech.”

Ken Rim, an IBM researcher working on strained silicon, said his group was just beginning to consider new device concepts. He added that chips made with strained silicon could operate at lower voltages, making the material useful for small and portable devices.


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