Intel skips along Moore’s Law tightrope with improved chip process

Mark A. DeSorbo

HILLSBORO, OR—INTEL.CORP.'S 300 MM chipmaking processes are the smallest ever, and while it continues to push the Moore's Law envelope, cleanrooms and contamination control practices remain relatively unchanged.

Even as the new 90-nanometer (nm) process was unveiled, Intel had already begun work on a new facility, known as D1D, a ballroom-style cleanroom equipped with minienvironments, where research and development of even tinier, next-generation geometries will take place.

The ballroom-style cleanroom is a departure from Intel's preferred bay-and-chase design, says Tom Garrett, Intel's D1D fab manager.

“We decided we saw some good advantages to the ballroom,” he says, declining to elaborate on layout specifics. “The big finding of the ballroom is we can get more tools in the ballroom than we can in a bay-and-chase.”

Air in the D1D fab will move downward, passing through numerous filters and through the floor into a subfab. The D1D design, Garrett says, also allows heat from boilers to be recycled, reducing the number of boilers and decreasing nitrous oxide emissions by 80 percent.

While the DlD facility is a ballroom design, it will borrow the same ISO Class 4 environs and sub-ISO Class 3 minienvironments as the D1C facility, a bay-and-chase facility that is home of the 90-nm process.

The only major change at Intel's newest facilities is how 300 mm wafers are handled. Cleanroom personnel will no longer handle wafer pods, mostly because they weigh close to 20 pounds. Instead, front-opening unified pods (FOUPs) will transport wafers to and from tools along an overhead-automated rail system.

“The pods are heavier than what you would want people lifting,” Garrett adds.

Once a pod reaches a tool, it is lowered to a load port of the tool by an elevator mechanism. At the load port, the pod is sucked up against the tool and seal, triggering a door to open so the pod is automatically loaded into the minienvironment.

The deployment of the automation has resulted in an ever so slight degradation of cleanroom cleanliness as well as a decrease in personnel.

“We do not need cleanrooms at traditional cleanliness levels, but you can't degrade them that much, and we're still running at ISO Class 4,” Garrett adds. “There are a few less people in the cleanrooms, but we still have tools that need to be repaired and data that needs to be entered. Processes have not progressed to the point to eliminate people.”

Intel, however, continues to test the boundaries of Moore's Law for matters of cost and practicality.

“Microns are too big,” says Mark Bohr, Intel's director of process architecture and integration, adding that over half of the company's microprocessors were produced at the 0.13-micron, or 130-nm level during the second quarter of 2002.

The new 90-nm process features transistors with a 50-nm gate, 10 nm less than the transistors in Intel's Pentium 4 processors, Bohr notes. The transistors also feature gate oxides that are less than five atomic layers, or 1.2 nm thick.

Intel has also implemented its own high-performance strained silicon method into the 90-nm process, which Bohr says provides faster electron flow and yields 10 to 20 percent increase in performance.

“The 90 nm process will be ramped to high volume in D1C and transferred to other 300 mm fabs, starting in 2003,” he reports.

With that ramp up of 90-nm production starting in 2003, Garrett urges that continuous improvement in process tooling and cleaning procedures is needed.

“It has to get better and better and better,” he says. “The qualities of the materials that are being used to make these tools must improve, and process tools must continue to get cleaner because it's within the tool that a particle has the chance to get on a wafer.”

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