The atmosphere of the 22nd BACUS Photomask Symposium, held recently in Monterey, CA, was oddly upbeat, with a record 156 papers and high attendance, in spite of depressed industry conditions. The mask industry has been hard hit by the slow shift to 130nm and beyond, since most of industry revenue comes from such advanced reticles.

However, as Naoya Hayashi of Dai Nippon Printing (DNP) reported, the advanced pattern generators needed to print such masks cost four times more than previous equipment but run 10 times slower, resulting in a fortyfold cost increase. Yet the advanced technology supports only a 5X reticle price increase from the 500nm node.

The keynote speaker, Buno Pati of Numerical Technologies, hailed the challenge of manufacturing production-quality, subwavelength masks as an opportunity for the maskmaking industry to recover its former prominence in semiconductor manufacturing and capture more of the value it creates. Pati made the case for the maskmakers to leverage the investment made and drive the semiconductor industry.

Many changes will be needed to profit from the opportunity, however, and some of them will conflict with the interests of established players. To thrive, the mask industry must take control of its own agenda, noted Pati.

Of special concern is the potential to lose ASIC customers. He urged the industry to accommodate this valuable market segment, particularly by reducing the number of copies of die on critical layer reticles for low-volume production runs, where, he notes, the higher cost of wafer lithography is more than offset by the savings in mask costs. He also called for greater communication between IC designers and mask designers.

“Communication by itself won’t solve the problem,” stated Dinesh Bettadapur, president and CEO of ASML MaskTools. “We need an infrastructure to promote better understanding of each other’s domains. People have become so specialized that we need an integrated way of looking at the problem — local optimization in a global context.”

Even the old standby used in other industries — systems engineering — won’t solve the problem, according to Bettadapur, because the differences between the disciplines are too great. Bettadapur is more optimistic when it comes to a discussion of maskmakers enabling their ASIC customers’ success. “ASIC designers won’t become FPGA designers overnight,” he explains. “There might be a market share loss, but ASICs won’t go away anytime soon.”

One highlight was the roll-out of the replacement for GDSII as the data format for specifying masks. The new proposed 64-bit stream format, called OASIS, is dramatically more efficient in almost all contexts and has been widely endorsed, but realizing the full benefit of updating the bit-level layout paradigm will require implementation of a “universal data model” also being developed by SEMI. According to Tom Grebinski, SEMI Data Path Task Force Chairman, $4-6 billion is being lost each year because of inefficiencies and poor communication embedded in the data path. Replacing GDSII is just a start toward more productive practices.

Selete and SEMI had been developing competing standards, but during the conference Selete announced that, after collaborating with task force members, it now supports the SEMI effort. Grebinski said Selete plans to refocus its efforts further downstream to optimize the native intermediate formats used by electron-beam mask generators.

“Selete will be supporting the development of OASIS and SEMI will be offering help to Selete with development of its data link to OASIS and with ongoing concerns of Selete’s membership,” Grebinski said.

Pattern generators

The first of the new generation of fast stepper-like laser pattern generators has been delivered to DuPont Photomasks, according to Tor Sandstrom of Micronic Laser Systems. The tool benefits from some of the advantages of the partially coherent imaging used in wafer exposure tools, but cannot allow its illumination to be optimized for any particular pattern.

Nevertheless, by tilting the micromirrors that form the images beyond the level that gives “dark,” the system can produce destructive interference between pixels comparable to attenuated phase shifting masks, improving contrast and resolution.

Tom Newman of Etec Systems/Applied Materials described an extension of the MEBES eXara to a “raster-shaped beam” technology that allows real time proximity correction and should support 50nm photomask development — with 4nm precision and less!

Inspection tools

In a potentially major development, Anja Rosenbusch of Etec Systems/Applied Materials described a new 193nm aerial image inspection system that employs technology similar to the Zeiss MSM-193 review station.

These so-called AIMS tools emulate the optical performance of the actual exposure tools and identify defects in the aerial image, rather than the mask itself. Masks incorporating strong phase-shifting technologies require inspection on such a tool. The new Israel-developed Etec system promises to detect 60 degree and 120 degree phase defects as well as any other defects capable of causing 10% CD variations at the 120, 90, and 65nm nodes, with 2-hr turnaround time for a 10cm square inspection area.

Initial results on an AIMS tool engineered for 157nm were reported by a team from International SEMATECH, Zeiss, and Infineon. Because of the need to protect everything from oxygen and moisture, the entire a-tool lives in a glove-box. Targeted for the 65nm and 45nm nodes, this inspection system has already shown adequate laser beam stability and is overcoming the challenges of laser speckle in the image.

Larry Zurbrick of KLA-Tencor described a phase-contrast enhancement method (“teraphase”) that allowed new KLA mask inspection tools to detect phase defects more efficiently using transmitted light alone.

In another paper, Dan Bald and a team from Intel and KLA-Tencor described the DIVAS system, which saves and analyzes the images of defects seen by mask inspection tools. Subsequently applying simulation technology allows the importance of different anomalies to be judged.

For EUV masks, Alan Stivers of Intel described a multibeam confocal microscope inspection system capable of detecting 93% of programmed surface-bump defects on multilayer substrates. Such defects, due to buried particles or other causes, are expected to be printable even if they are only 1.25nm high and 60nm across. The good news is that the 33 beam optical tool could detect such a large fraction of the programmed defects. The bad news is that it also found many, many more apparently real defects than had been anticipated; these would probably print on wafers. Thus, further study — and possibly actinic inspection — may still be needed.


Repairing the anomalies detected on photomasks has long been problematic. Some repair processes do more harm than good. Volker Boegli of NaWoTec GmbH in Rossdorf Germany described a gentle e-beam enhanced chemistry approach to fixing clear and opaque defects.

By locally dissociating an organo-metallic precursor with a tightly focused electron beam, NaWoTec deposits platinum and other metals, even forming bridges on stencil masks. TaN, an absorber used in EUV lithography, can be etched using e-beam activated XeF2, but for now, chrome defects cannot be removed.

Alfred Wagner of IBM described an innovative laser method to remove chrome with femtosecond laser pulses. When such short pulses are focused to high power they directly break chemical bonds, atomizing materials without thermal damage. According to Wagner, IBM uses the second-generation MARS2 tool as its primary means of repairing 248nm and 193nm masks.

The highly automated system can remove material gently in “nibble” mode with 8nm 3sigma edge placement accuracy, carve 80nm holes and trenches, and keep transmission loss below 2.5%, according to Wagner. What was not presented was any feasible scheme to commercialize a turnkey version of the system.

Robert Muller from LSI Logic described a management system for dealing with photomask defects in a wafer fab. In real life, it sometimes pays to tolerate defects, according to Muller. The challenge is to identify those cases efficiently. LSI developed a web-based detection, classification and dispositioning database tool to help operators of mask inspection stations make the best decisions. Sometimes, when a multichip reticle has a killer defect on one die, it is better to accept the yield loss than to order a new reticle.

“Virtual inking” identifies the known bad die produced by such a defect and saves cost by eliminating further processing. Using this system, LSI entirely eliminated rejections of new photomasks (and related delays and cost increases) for three months.

When good reticles go bad

Kaustuve Bhattachryya of KLA-Tencor described syndromes where DUV exposure caused soft defects to form on the pellicle-protected reticle surface. Most defects caused an approximately 13% reduction in transmission, but even that could kill yield. Chemical analysis of the material on the surface revealed ammonium sulfate, cyanuric acid, and an unknown organic. The speculation was that the DUV exposure was causing vapor-phase photochemical reactions among the species outgassing into the confined pellicle-reticle space. The less-volatile products deposited on the reticle surface, whereupon crystallites nucleated more rapid deposition.

After an unpredictable number of wafer exposures — perhaps 700, perhaps nine — the reticles became unusable and had to be cleaned and re-pellicled. This phenomenon bodes ill for 157nm lithography schemes involving nonremovable hard pellicles.

Panels and symposia

Hiroyoshi Tanabe of Elpida memory reported the results of a panel discussion on favored lithography strategy held at Photomask Japan in April. Participants there seemed skeptical of NGL, except possibly for the use of the Nikon PREVAIL system for writing 60nm contacts. The consensus seemed to be that ArF exposure would be used with RET for the 90nm and 65nm nodes, with 157nm exposure being introduced with strong RET in 2007. The RETs required to print acceptable images could prove very challenging to the mask industry and lithography-friendly layout will prove essential, at least according to the presentation made in Japan by Woo-Sung Han of Samsung.

One entire session was a symposium on “130nm and Beyond: At What Price?” organized by Walt Trybula of International SEMATECH. Trybula pointed out that the model for reticle prices was different from that in the textbook: while prices might fall early on for a given technology, they rise as volume and quality expectations grow. This apparent inverted learning curve feeds widespread dissatisfaction and may reduce future leading-edge mask volumes.

Also at the session, Brian Grenon described the realities behind over-optimistic cost projections: Early on, yield is terrible — 8% or so — and the real cost of each delivered mask plate is $400,000 or more. No one actually charges that much, so leading-edge customers get a subsidy from the maskmakers. In return, they loosen specs and accept delays. After three years of practice, the maskmakers improve the yield to 27% or so, reducing real costs to $50-80,000/delivered plate. At that point, however, specifications tighten and delays become unacceptable, raising costs. Thus it is entirely possible that the price of a typical 130nm node mask set will exceed $1 million, with 90nm and 65nm mask sets costing $1.6 million and $2.9 million respectively. These costs are driven by low throughput of pattern generators and low yield. Effective repair technology would cut them dramatically, according to Grenon, but mask repair technology lags one full generation behind and has not been perceived as profitable for the tool companies.

Tight specs and other developments

“After years of talk and no action, this year’s papers include some work to lower mask costs,” noted Griff Resor, president of Resor Associates. In response to the presentations by IMEC and Toshiba on flexible mask specs, Resor stated, “Finally it appears that the looming high cost of mask sets is stimulating ‘smarter’ mask specs that permit good results and better mask yields, even as dimensions and tolerances shrink” — although Resor prefers to call them sensible mask specs. For example, Toshiba showed that increasing the allowable range of values for each individual variable by trading off CD to target and CD variation resulted in a 20% increase in mask yields for 130nm design rule memory circuits.

Kevin Cummings of ASML deflated expectations that future complex exposure tools would enable simpler masks with lower prices. According to Cummings, the least expensive mask type used by the next generation of tools will always cost at least as much as the most costly one used previously, if only because of its tighter specifications. In particular the materials issues of 157nm and EUV lithography will bump mask costs above the current exponentially growing trend line. All of this is likely to kill the ASIC chip segment near the 65nm node, according to Cummings.

Other speakers illuminated the problem from different viewpoints. Ben Eynon of Photronics pointed out that the Pareto charts showed that the dominant cause of mask rejection was “fear,” not a defined printable defect. He recommended improvements in defect terminology and coding to permit less-than-perfect masks to be accepted. Keith Standiford pointed out that a company had to anticipate a $1 billion market for a new generation of pattern generation tools in order to justify the R&D expenses. Standiford felt that there were too many suppliers, some of which enjoy R&D subsidies and thus can offer unrealistically low prices. Once self-sufficient competitors are driven out of a market segment, however, these “stupid competitors” get smart, raise prices and gouge their customers! He also pointed out that resist and other materials suppliers to the maskmaking industry have an even more dysfunctional business model and will not be able to provide the roadmap-required process improvements to what amounts to a low-profit niche market.

Jim Wiley observed that the market for maskmaking tools is getting smaller, not larger, even though more super-slow pattern generators continue to be shipped. Companies making low-cost ASIC chips are not migrating to costly and uncertain 130nm technology, according to Wiley. One projection he quoted was that the entire world demand for semiconductors could someday be filled by 20 300mm fabs in low-wage areas, mostly making commodity FPGAs! Under such circumstances, does it make sense for anyone — even International SEMATECH — to subsidize reticle equipment maker R&D?

At the end of the meeting Trybula identified the mask cost explosion as “a symptom of low throughput and yield, not the underlying issue,” and summarized the panel consensus for International SEMATECH. Even after three days of meetings and an extensive overview of business model challenges, however, the symposium attendees did not seem likely to rise to the challenge posed by Buno Pati at his keynote address: they simply will not try to drive the technological agenda themselves. Help, of a sort, may be at hand, though. Dr. Martin Peckerar of the Naval Research Laboratory held meetings with industry figures in hopes of advancing the plan he announced at this summer’s Advanced Reticle Symposium to set up a federally sponsored National Reticle Research Facility. Skeptics felt that such an initiative would do to maskmaking what previous federal support efforts did to the American exposure tool industry (send it elsewhere).

In discussions after BACUS, IMEC’s Kurt Ronse, director of the lithography department, silicon process technology division, said that because of the organization’s need for advanced masks in its Industrial Affiliation Program, it experienced early on the difficulties associated with tight specifications. The research consortium is active in SEMI’s Mask Qualification Terminology task force. “The task force has as its charter the realization of a uniform set of definitions for mask qualification parameters — an important requisite for realistic specifications,” explained Ronse.

The idea of focusing on the image on the wafer instead of the mask was a constant theme throughout the conference. The tendency to view masks as commodities was engendered during the “5X holiday.” Described by Tom Blake, VP of marketing at DuPont Photomasks, this was a period of time starting in the late 1980s when lithography went from 1X imaging to 5X imaging almost overnight. “Photomasks became like a commodity with barriers to entry being low — a service, price-driven business,” explained Blake. “Customers demanded inflexible specifications. Those days are long gone.” Because photomasks bring greater value, there is a greater need to work collaboratively and earlier in a chip’s design phase, an impetus for DuPont Photomasks purchase of BindKey Technologies’ electronic design automation software business earlier this year.

Market musings

Photronics’ CEO Dan Del Rosario was asked whether the market will essentially be bifurcated such that only a few major IDMs and foundries will be able to afford moving to 90nm and below with everyone else lagging way behind. Noting that 130nm is less than 1% of wafer revenues today, Del Rosario stated that, “the 130nm node is a major inflection point in the industry. There’s been a lot of focus on masks because of the extension of 248nm…if you don’t know what specifications and stepper you’re going to use…and then project costs using a 248nm stepper, the cost estimate won’t be valid.” He thinks the bifurcation is more a function of the lithography process at the wafer end.

Asked to comment on the larger economic issue of corporate IT spending drying up and the flattening of consumer spending, which is about the only driver of the industry now, Del Rosario stated that consumer products are at 0.18 micron and above, so corporate IT spending has to come back because it fuels the leading-edge products.

Mask quality survey results

Kurt Kimmel, ITRS mask strategy program manager, presented results of the mask industry survey conducted in 2002. Curiously, although the SEMI North America-sponsored survey was sent to all maskmakers listed in the 2002 edition of the Mask Makers Handbook, there were only seven respondents: Compugraphics, DNP, DuPont Photomasks, IBM (captive), Intel (captive), Taiwan Mask Corp., and TSMC (captive) [1]. Among this group of companies, binary masks make up 95% of the total volume, in stark contrast to the amount of attention advanced masks (sub-150nm ground rules) receive at conferences and technical papers.

Kimmel reported that about 80% of mask volume is at the 250nm node (or larger) design ground rules. The figure shows the size and relationship of the photomask business with respect to the semiconductor and wafer fab equipment markets.

Magnification distribution at 4X is 60%, with 5X at 25% and 1X at 15%. Surprisingly, 79% of the market is not using OPC. Another stunning number: 18% of yield losses are due to human error — both administrative and manufacturing errors — suggesting that more automation in data handling, order processing, and production/process control presents an opportunity for improvement. Defects are the largest process-related yield loss mechanism at 50%. Other statistics: 46% of masks are repaired using lasers, 40% are not repaired at all, and 14% are repaired using FIB (focused ion beam).

The major issue of data file size explosion could be seen with the average size being 0.7MB, yet a maximum size of 18GB had been reported. Data preparation times averaged 1.6 hours, but 500 hours was the maximum reported. — M. David Levenson, Contributing Editor, [email protected], and Debra Vogler, Senior Technical Editor, [email protected]

1. B.J. Grenon, “MaskMakers Data Book,” 2002 Edition, published by Grenon Consulting, Inc., 2002.

After-dinner show

The traditional after-dinner show started with yet another award for widely appreciated BACUS founder and show organizer, Jim Reynolds, who has spent the last year trying to retire. Previously, at dinner, he received the SPIE President’s Award from James Harrington, who had no idea what lay ahead. The show proper began with Frank Schellenberg speaking humorously — comprehensible Japanese (with projected subtitles) as he impersonated Chairman Kaga of “the Iron Mask Maker Show.” The Muppet-like Iron Maskmaker — Swedish (Greg Hearn) won a competition with Emeril (Stuart Lyle) to make the mask set that best featured the theme ingredient — 65nm potatoes!

Government attempts to support maskmaking (and divert attention from previous screw-ups) were satirized in a “Department of Chromeland Security” skit.

The hit of the show was perhaps the spoof sales presentation for Mentor Graphics new data fracturing technology, presented by Steffen Schulze, who is actually in charge of the Caliber MDP product. According to the demonstration on the sales video, the new product is actually a large sledge-hammer with a cubical head, capable of quickly fracturing any mask into bits, except that alternating PSMs require two passes! At the end, a large yellow cat drove the Mentor engineers away….

Compared to last year’s symposium — held in the aftermath of Sept. 11 — the 22nd BACUS Symposium was remarkably upbeat, with attendees looking forward to confronting the challenges ahead even as volumes and margins appear likely to shrink. The maskmakers glory a bit in their current difficulties, but believe, perhaps more than other industry segments, that they have survived the worst!


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