Wafer-level Packaging and Test, Technologies and Trends


The term “wafer-level packaging” (WLP) entered the microelectronics industry's lexicon in the late 1990s. As the advantages of area-array integrated circuit (IC) pin configurations have become clear, the industry has been accelerating the movement in that direction for several years. The race to smaller area footprints for the IC is an ongoing compromise among several cost drivers. As the real demand for the ultimate in size reduction occurs in portable consumer products, cost pressure becomes the product differentiator.

One subtle cost-balancing act relates the size and pitch of the IC device to the cost, quality and reliability of the assembly processes. Devices with array pitch less than 0.75 mm require special considerations to successfully integrate into a high-speed SMT assembly process. Additionally, fine-pitch devices require sophisticated microvia technology for routing signals on the printed circuit board (PCB). Thermal mismatch between the IC and the board will require underfill when minimizing the area footprint for a given number of IC leads.

As a consequence, the IC packaging industry is focusing attention on WLP, where the problems mentioned previously can be mitigated, as well as advantage taken of further cost savings through batch processing.

WLP is an advanced packaging technology in which the die interconnects are manufactured and tested on the wafer, then singulated by dicing for assembly in a surface mount line. The interconnects are characterized by wider pitch and larger ball structures than associated flip chip structures. Generally, the term flip chip is applied to those die with area pad pitch of less than 250 µm and ball diameters less than 120 µm. JEDEC has defined a “die size chip scale package” that describes the WLP phenomenon.1

Devices that are packaged at the wafer level are more generally termed wafer-level chip size packages (WLCSP). The chip pads are redistributed over the face of the chip, followed by the addition of solder balls, plated studs or some other area-array interconnect pattern. The redistributed pads can accommodate larger pitch and solder ball size. The relaxed pitch has distinct implications for applications of these technologies. The International Technology Roadmap for Semiconductors (ITRS) forecasts the various pitch measures for leading edge ICs as portrayed in the table.

ITRS forecast of minimum pitches of various mounting technologies for leading edge ICs.
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WLP Development and Deployment

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IC packaging is undergoing a fundamental paradigm shift with the effort to move from one-at-a-time mechanical assembly to mass fabrication directly on the wafer. This shift enables cost reduction-based batch processing much like that which IC fabricators historically have exploited. Used mainly on small die, WLP is moving rapidly into the mainstream. Figure 1 shows the IC packaging unit growth forecast through 2005.

Figure 2 shows which device types are thought to be good candidates for WLP approaches. A large percentage of these devices are integrated passive components (IPC), which are in three general categories: resistors, capacitors and inductors. Combinations of these devices provide for timing loops around analog devices, tuning structures around radio frequency (RF) circuitry, filters and resistive loads on differential pairs, among other applications. Passive integration is evolving into a form of filtering and electromagnetic-interference (EMI) suppression devices that may incorporate capacitors and inductors in a single package.

WLP Strategy and Reliability

Numerous issues come into play when considering committing to a WLP process. Die size, input/output (I/O) numbers and yield all directly impact the cost for packaging an individual device. Of course, for a WLP scheme to be feasible, all I/O must fit under the periphery of the die at the desired pitch. Figure 3 shows the minimum die size required to fit selected I/O arrays for certain pitches.

Figure 2. Forecast showing types of products that will benefit from WLP.
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Additionally, because small, low I/O devices are the most space inefficient devices used in systems today, WLP creates an additional bonus. Many of these devices traditionally have been packaged in lead frame or area-array packages. For these packages, a fixed sized contour or exclusion zone is required as a package adder to the die size to accommodate such requirements as wirebonding, overmolding and leads in the case of leaded packages. This fixed space overhead results in poor packaging efficiency, especially for smaller die. Consequently for smaller die, the WLP format is a particularly attractive option.2

For small die, the thermal mismatch between the silicon and its circuit board substrate is less problematic because of the small distances involved. A chief limitation to the pin count for bumped WLPs has been less than about 60 balls because of limited solder ball fatigue lifetimes. As the pin count grows, the distance between the center and the farthest solder ball — the distance to the neutral point (DNP) — grows longer and the stresses on these outer solder balls cause cracking during thermal cycling. The industry standard is for chips assembled to circuit boards to have a Weibull 50 percent lifetime of 1,000 cycles for temperature excursions from -40° to 125°C, at one cycle per hour.3 These low I/O devices, coupled with the WLP's larger pitches and ball sizes, reduce the need for underfilling the device after board assembly. Besides the obvious cost adder to perform the underfill step, introducing underfilled area-array components raises new issues regarding their reworkability because most current underfill materials are polymeric thermoset materials that are not reworkable.4

Burn-in and Test

Several choices are becoming available to meet the need for equivalent WLP quality and reliability that is customary for packaged ICs in the industry. The most cost-effective test solution is a single insertion at the wafer level that will fully test for defective parts and screen for infant mortalities. While this goal is unlikely to be reached for all ICs all the time, it is achievable for a number of device types, especially the small I/O, small size die discussed previously.

A cost-effective test strategy is based on fab process maturity, device type complexity, yield management effectiveness and an appreciation of the application domain requirements. Test strategies range from no test at all to full testing of all AC and DC parameters, as well as functional and structural testing. Testing done at the wafer level traditionally has been a minimal test to simply ascertain gross failure. However, with WLP devices, the entire final test suite should be performed at the wafer level to realize cost efficiencies. Fortunately, the trend in the industry is to do more testing at the wafer level.5

Figure 3. Plot of minimum die size for various I/O per die at several pitches.
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IC manufacturers use screening procedures to remove weak devices from a lot before shipping to the customer. Screening ICs is done by applying stress to the devices and using operational tests to detect failures. Stresses applied may be electrical, thermal or mechanical; the stress causes weak devices to degrade, while causing no detectable damage to devices within the normal population. Several technologies are available if screening is needed to achieve reliability goals:

  • Wafer probing with reliability screens
  • Test and burn-in using test socket
  • Full wafer burn-in and test
  • Wafer probing with reliability screens.

Wafer probe methods are being developed by IC manufacturers to increase the probability of eliminating defective ICs as well as identifying infant mortalities in a lot prior to shipping. This has the potential for significant cost savings for the latest generation ICs, regardless of the packaging formats used. These wafer probe test and stress screening methods are effective for the acceleration and detection of various types of defects for today's ICs.

Test and Burn-in Using a Test Socket

Advanced IC packaging demands smaller pitch capability in test and burn-in sockets to accommodate WLP formats. Burn-in testing of these devices has resulted in the development of new types of miniaturized contacts for area-array pitches greater than 0.75 mm. These sockets have been accepted and users now are purchasing significant numbers of sockets for the burn-in testing of memory die.6 The move to 0.5 mm pitch packages is challenging suppliers to develop new types of contacts that are mounted directly under the die balls rather than to the side.

Wafer-level Burn-in and Test (WLBT)

WLBT typically is understood to incorporate a full wafer contactor, either a probe card or sacrificial layer of metal that is deposited on the wafer and then removed. Input nodes on each chip may then be “toggled” to exercise the devices. The voltage applied may be significantly higher than the data sheet maximum, which provides additional stress to cause devices with certain weaknesses to fail. The high voltage, along with higher temperatures, accelerates weak devices to fail. Such devices then are detected with functional or parametric tests and eliminated from the customer shipment. WLBT has the potential for greatly simplifying the back end of an IC fabrication line.

The main obstacle to implementing a WLBT process is development of a full-wafer contact technology with the process capability required for manufacturing. Contact process capability is a function of not only the contactor technology performance but also the burn-in stress requirements for a given product. There are several programs worldwide that are working on developing solutions to the full-wafer contactor problem.

Contact failures during burn-in result in reduced process yield and, if not detected and captured, can lead to an increased product field failure rate. Contact capability requirements are established to ensure that product quality levels (field failure rates) are maintained if not improved by WLBT. If this goal is achieved, then yield loss due to failed contact will be almost nonexistent.


  1. JEDEC Standard 95-1, Design Requirements for Outlines of Solid-state and Related Products, Section 7, Die-size Ball Grid Array Package (DSBGA), February 2001.
  2. T. G. Tessier et al., “Technologies and Trends in Wafer-level Packaging,” Future Fab, Volume 11, June 2001.
  3. Eric Bogatin, “All Dressed Up and Nowhere to Go,” Semiconductor International, May 2002.
  4. David Bergman, “Emerging Flip Chip and Wafer-level CSP Technologies,” Surface Mount Technology, July 2001.
  5. Art Wager, “Wafer Probe Tests and Stresses used for Quality and Reliability Improvement,” 8th Annual KGD Packaging and Test Workshop Proceedings, September 2001, www.napakgd.com.
  6. James Forster, “Chip Scale Package Burn-in Socket Technology as Pitches Move to 0.5 mm,” Future Fab, Volume 9, January 2000.
  7. Dennis R. Conti and Jody Van Horn, “Wafer-level Burn-in,” ECTC 2000 Proceedings, May 2000.

Larry Gilg, managing director, may be contacted at the Die Products Consortium, 3908 Avenue G, Austin, TX 78751; (512) 452-0077; Fax: (512) 452-5141; E-mail: [email protected]; Web site: www.dieproduct.com.


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