“Hot-bottom”Ceramic Package

An old concept called a “hot-bottom” package is revisited here. This study entailed the fabrication of ceramic-based, microelectronic packaging structures with enhanced thermal conductivity. For identification, this design is referred to here as a 'thru-mount' package, in which, in this case, a pin-grid array (PGA) type of package has its die attach region base replaced with a material with higher thermal conductivity than the original package body material (Figure 1).

Figure 1. Cross-section of a package with a “false bottom” of high thermal conductivity material.
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Experiment Details

For the evaluations, cavity down, 169-pin, aluminum oxide, PGA packages were used. Holes 0.500 x 0.500″ with 0.020″ corner radii were ultrasonically machined cleanly through the center of the PGAs using equipment from Bullen Ultrasonics. Separately, a square pattern centered on the underside of the alumina packages was metallized so that after ultrasonic machining of the window in the package, a metallization boarder would remain. This would serve as a solder attachment region for the thermal substrate squares using a Kovar attachment ring. Separately, each thermal substrate was sputter metallized with 1 µm of Cr/Ni on each face and then post-electroless Ni plated. The total thickness of the metallization was approximately 4 µm.

Substrate soldering to the Kovar ring and the Kovar ring to the bottom seal ring was performed using 63Sn/37Pb solder cream with rosin flux. Soldering was performed at 185°C after first preheating the assembly to 120°C.

The packages were assembled without lids, with units made with five different substrate materials: CVD diamond, copper, aluminum oxide-reinforced copper (“Glidcop” from SCM Metal Products), copper/tungsten composite and aluminum nitride (AlN).

The table shows thermal and mechanical material properties of the substrates used in this evaluation.

Figure 2. Schematic diagram of thermal test die with bonding sites.
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A thermal test die (Figure 2) was attached to each substrate, and the devices were appropriately wire bonded (Figure 3). Thermal testing was performed using infrared (IR) thermal mapping with the device under different power levels and backside airflow rates.

Figure 3. Overhead view of the die mounted into the package and wire bonded.
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Power Testing Results

The evaluations were performed using packages with five different high-thermal conductivity materials, plus reference samples of the unmodified aluminum oxide package. The thermal die was tested to 5 and 8 W of power. In the case of AlN, 10 W was used initially to investigate the high power capability of the package modification. This gave rise to maximum junction temperatures above 200°C in still air, so the test setting for high power then was switched to 8 W.

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The two primary parameters measured under device power were the maximum junction temperature and the thermal resistance values of the device when referenced to ambient, both under still and forced air conditions.

All tests were performed for still air, 100 and 200 linear feet per minute (LFPM) of airflow in order to observe the effect of air flow on a package design's performance. There was no attached heat sink, While the inputs were set at 5 and 8 W for testing, actual values differed from these once a given test specimen reached steady state operation.

In looking at the extreme case, the control package (i.e., an unmodified aluminum oxide package) showed a maximum junction temperature above 200°C for 8 W of power and no airflow. The worst case for package Ref. 8 W-#2 under test conditions of 0, 100 and 200 LFPM, the maximum junction temperatures were 179°, 166° and 155°C, respectively. The corresponding thermal resistance values were 20.3°, 18.2° and 16.3°C/W. Using CVD diamond (the substrate with the best thermal conductivity tested), the maximum junction temperatures were 140°, 126° and 111°C, for 0, 100 and 200 LFPM. The corresponding thermal resistance values were 15.2°, 13.0° and 11.0°C/W.

For 8 W testing in still air, diamond showed an average of 53.4°C temperature reduction when compared to the control packages. AlN delivered approximately 15°C in temperature drop. The other substrates showed values up to about 32°C in temperature drop for the same conditions.

For 5 W input in still air, diamond showed an average decrease in maximum junction temperatures vs. the control specimens of 26.1°C, and the other substrates resulted in average savings of 2.5°C (AlN), 7.7°C (Cu/W), 13.4°C (Cu) and 12.7°C (Glidcop) compared to the controls. Lower maximum junction temperatures were found for 100 and 200 LFPM, but the temperature changes were not always greater.

Thermal Mapping

Figure 4. Thermal map for reference/control part with Al2O3 base, 8 W and 100 LFPM of backside airflow.
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Figures 4 to 6 are thermal IR maps of the ICs for the following illustrative conditions: Al2O3 at 8 W with 100 LFPM, Cu/W at 8 W with 200 LFPM and CVD diamond at 8 W with 100 LFPM.

Figure 5. Thermal map for Cu/W, 8 W and 200 LFPM.
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Review of numerous IR maps showed, as was expected, that those devices mounted onto substrates of higher thermal conductivity exhibit cooler temperatures across the die face for any given airflow rate.

Figure 6. Thermal map for CVD diamond, 8 W and 100 LFPM.
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The IR images, especially Figure 5, show some asymmetry in the temperature contours. This probably is due to a slightly nonuniform bondline thickness of the conductive epoxy, although it does not seem to affect the maximum junction temperature. Also, the local rises near the periphery could be due to voids in the die attach material, although again, this does not affect the maximum temperature of the device significantly. It is worth noting, though, that these kinds of process issues can affect the device's performance.

For the overall system design, the designer also must be aware of the substantial cost variation for the different materials. There are likely to be cost/performance tradeoffs required in the design phase. It also can be noted that no consideration was given in this study to substrate expansion coefficient and, therefore, thermal stress imparted on the die with the different materials. These thermal-mechanical effects also could be a factor in the package's ultimate design.


The replacement of the bottom of an aluminum oxide package's die attach region with a substrate of higher thermal conductivity results in substantial thermal dissipation improvement from a mounted thermal test die. Under testing with power up to 8 W, for example, AlN, Cu/W, copper, Glidcop and diamond substrates showed lower maximum junction temperatures on the die by 16.8°, 31.3°, 27.8°, 27.6° and 43.4°C, respectively, for 200 LFPM of airflow on the package's backside when compared to reference/control samples. The trend for lower temperatures across the die and corresponding lower thermal resistance values is evident. Varying from still air to 100 and then 200 LFPM resulted in lower junction temperatures but not always higher differences compared to the control.

* This research was funded under NASA SBIR contract #: NAS5-38061.


The thermal testing was performed by Seelink Technology, San Jose, Calif., and the CVD diamond substrates were procured from Crystalline Materials Corp., Phoenix.

James Intrater may be contacted at Oryx Advanced Materials Inc., 46713 Fremont Blvd., Fremont, CA 94538; (510) 249-1157; Fax: (510) 249-1159; E-mail: [email protected].


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