Wafer-scale Encapsulation: Controlling MEMS Packaging Costs

Microelectromechanical systems (MEMS) technology quickly made the transition from innovative concepts to practical demonstrations and on to early products. The speed of this transition was based on an ability to leverage the manufacturing base of the integrated circuit (IC)industry: plant, equipment, tooling, processes, materials and people.

While initial MEMS technology success is based on similarity to the IC industry, current problems limiting MEMS market growth are rooted in fundamental differences between MEMS and ICs. Nowhere are these differences greater than in packaging and assembly. It is commonly cited that packaging accounts for 80% of the cost of a MEMS device, and these costs have shut MEMS out of many mainstream product opportunities.

The crucial differences between ICs and MEMS include the following:

  • ICs are essentially flat; MEMS typically are not.
  • ICs depend on effects buried beneath the surface of the IC; MEMS generally are surface effect devices.
  • ICs have no moving parts; MEMS typically move.
  • ICs are built in a way that makes them relatively insensitive to their environment before they exit the carefully controlled world of the IC foundry in wafer form. MEMS, in wafer form, are sensitive to their environment until they are packaged. This makes every post-fab MEMS handling step — wafer dicing, placement in a package, formation of electrical connections, package closure — different from IC handling and very expensive.

The key to MEMS packaging

ICs are passivated before they leave the fab. This passivation allows less costly environments and tooling to be used for packaging and assembly operations without compromising yield. The same approach must be used for a cost-effective approach to packaging MEMS. Wafer-scale encapsulation must be used to create a device scale hermetic enclosure (“headspace”) around the active MEMS elements before the MEMS wafer leaves the MEMS foundry. Until now, attempts to achieve this have presented a variety of compromises.

For widespread MEMS commercialization, numerous encapsulation criteria are important:

  • Encapsulation must avoid temperature ramps or chemical environments that will compromise MEMS performance and reliability.
  • Controlled headspace chemistry is essential for device reliability. This establishes encapsulation criteria for hermeticity, permeation and outgassing.
  • Low-cost encapsulation requires tooling that will scale as wafer size scales. As the IC industry continues to show, large wafer economics drive small wafers out of the market.
  • MEMS devices depend more on the mechanical properties of materials than ICs; thus MEMS encapsulation must not change the stress distribution in the device's active region.
  • Material selection for encapsulation must support a wide range of product criteria, such as transparency for optical access or low dielectric loss for radio frequency (RF) applications.
  • Encapsulating materials must support normal foundry processing steps to provide electrical contacts for wire bonding or bumping options.

Wafer-scale MEMS encapsulation

Ziptronix's wafer-scale encapsulation technology creates MEMS die that may be handled conventionally and, therefore, can be integrated readily with other system components. The process encapsulates MEMS at the wafer level in the MEMS foundry, reducing the expense of post-foundry operations and establishing a basis for standardized packaging (Fig. 1).

Figure 1. A portion of a wafer surface following Ziptronix wafer-scale encapsulation. This example is for an optical application, and the device cavity may be seen through the transparent cap.
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The key to the technology is room-temperature processing and a broad selection of material choices to establish a versatile basis for stress engineering, ranging from stress minimization to materials integration for temperature compensation or other performance enhancements. The nature of the bonding process eliminates epoxies or other materials that require curing cycles or create outgassing/permeation concerns. Instead, it uses established IC processing materials such as SiO2 to create a true hermetic seal. These process features, along with MEMS-specific variations in surface activation, allow users to establish and maintain proprietary headspace chemistries.

The process currently is carried out routinely on 200mm wafers and is readily extended to 300mm wafers.

Room-temperature covalent bonding

The proprietary technologies create room-temperature covalent bonding between material surfaces commonly used in ICs. Typical materials that are bonded include SiO2 (in various forms), Si, and Si3N4. (Process variations for other materials such as diamond-like carbon [DLC] are under development.) Note that GaAs or other exotic materials may be coated with SiO2 and bonded to Si ICs. From a bonding perspective, this is an SiO2 to SiO2 bond. Using this approach, numerous integration choices are available, including stacking of chips created with different processing technology.

Figure 2. A secondary electron micrograph of a structure bonded with the Ziptronix room-temperature covalent bonding process. The bond's interface is not visible.
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Figure 2 is an image of the cross-section of the company's bonded structure. In this example, a layer of nonvolatile memory has been integrated on a layer of logic. The image is formed using secondary electron microscopy, and in such an image, “features” are due to variations in electrons escaping from the surface. Unlike standard light-based images, these electron-based images are sensitive to variations in chemistry and bonding beneath the surface. The image shown contains several conventional oxide/oxide interfaces formed by industry-standard oxide deposition processes in which an oxide layer is deposited on an identical, existing oxide layer. Note that the resulting interfaces are easily seen.

In contrast, the bonding interface created with the company's technology is not visible, indicating chemical and structural homogeneity through the bonded interface. This bonding at the interface is equivalent to the bonding in the adjacent bulk materials. Such an interface shows no anomalies. Vias may be etched and filled or sidewall oxides formed as if dealing with a single homogeneous material.

Materials to be bonded are processed by chemical-mechanical polishing (CMP) to establish a planar surface where the bond is to be formed. For convex MEMS applications (where the MEMS structure extends above the surface of the wafer), this planarization step typically occurs early in the fabrication flow of the MEMS wafer. The cap wafer is similarly planarized. The fraction of the surface required for bonding is small. A narrow rim (<200µm) around the device will suffice. Relief structures are included routinely in the cap wafer to achieve headspace.

Process compatibility

Many process chemistries for bond activation have been developed. MEMS applications may involve a moving mirror in which reflectivity or stiction concerns dominate, RF applications in which proprietary contact coatings must be preserved, or a SAW application involving stringent criteria for dimensional control of the comb metallization patterns. In these cases, there are process options to ensure compatibility with active device structure requirements.

Packaging options

By creating a device scale hermetic cavity, the company's process creates many opportunities for form factor reductions. Conventionally, following special handling for dicing and die placement, the MEMS die is wire bonded inside the hermetic package before placing the “lid.” In contrast, Fig. 3 shows that the space enclosed with the MEMS device includes only the active device. Contact areas, wire bonding structures, die-attach materials, etc. are external to the hermetic volume, so materials and processes associated with these structures cannot compromise the MEMS device. This reduces the need for special handling of the MEMS die, cutting costs while simultaneously improving the post-foundry yield.

Figure 3. Schematic of an encapsulated MEMS device configured for wire bonding (dimensions in µm).
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Bumping options are also available. Bond strength is such that the encapsulated wafer may be aggressively thinned (by backgrinding or CMP). This wafer-scale thinning allows via access to the escape metal as shown in Fig. 4, where backside access is used. Other variations support frontside bumping. In Fig. 4, the bump points are supported by the solid column of material in the region of the seal, such that the cap provides support for assembly. With this approach, wafer-scale processing creates chip-scale, hermetic packaging of MEMS devices ready for bumping. The only materials exposed are the contact points, cap and underbump preparation.

Figure 4. A flip chip configuration for wafer-scale encapsulated MEMS devices (dimensions in µm).
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Economics: the bottom line

Today, MEMS are dominated by packaging costs. Virtually nothing is “standard.” Every step in the back end involves special handling and tooling. Despite precautions, each step creates a yield hit far beyond that expected for a comparable IC operation.

In large markets, large volumes have enabled product-specific “standards” to emerge. For most MEMS applications, however, the strategy has been to perform die-level assembly in a ceramic box, insert some desiccant and perhaps something for lubricity, solder on the lid, and live with the outcome. The result has been products where packaging and assembly often outweigh die costs by 4:1 or more.

Room-temperature, wafer-scale encapsulation addresses this challenge. For the first time, MEMS product wafers can be handled like IC wafers. This is the basis for developing broadly applicable packaging standards for MEMS.

Today, a MEMS die accounts for a small fraction of the cost of the packaged MEMS device. Soon, the package will account for a small fraction of the cost of the packaged MEMS device. Forecasters have long predicted rapid growth of MEMS markets; this technology is the type of advance required to move the growth forward.

Bob Markunas is VP of market development at Ziptronix, P.O. Box 14582, 3040 Cornwallis Rd., Research Triangle Park, NC 27709; ph 919/541-6153, [email protected]


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