Multichip Packaging, Business and logistical issues


Continuing functional enhancement of portable consumer and computing products challenges electronics industry OEMs to provide these products in smaller and lighter form factors. This places significant pressure on silicon device vendors to increase chip functionality and to place their chips into smaller packages. Significant advances in single chip packaging the last few years met this need, but now the pressure continues, resulting in increased focus on placing multiple chips into a single package.

Multiple chip packages (MCP) provide several advantages, including increased silicon density, reduced system cost and higher reliability. These advantages lead to a host of benefits and opportunities, such as greater functional density, improved board- and system-level production yields, lower power consumption (smaller batteries or longer battery life), and fewer and easier warranty and field repairs, not to mention simplified system design and modularization. These benefits encourage continuing MCP innovation, the latest technologies allowing integration of several chips into a single package in a wide variety of configurations.

Today, the limited adoption of MCP solutions results not from technical constraints, but rather from several nontechnical issues, namely business and logistics challenges related to the design and procurement of multiple chips for single package integration.

Figure 1. Typical two chip die-stacked package.
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MCP Benefits

Key benefits of MCPs include:

  • Accelerated time-to-market and time-to-volume production
  • Simplified product modularity/partitioning, functional enhancement and modeling
  • Reduced system cost through simplified printed wiring board (PWB) structures, higher assembly and test yields, and reduced logistics overhead
  • Improved product reliability.

Time-to-market acceleration results from removal of any need to design key functions at the product level. Only the interface between a specific, standardized MCP and the rest of the product functions remains necessary. This also impacts time-to-volume production by removing much of the prototype troubleshooting and design problem resolution from the product introduction cycle.

Having standardized MCP modules available for common functions greatly simplifies the design process, allowing product designers to focus their energy on tailoring products to their customers' needs rather than on making

certain that isolated product functions work properly. Also, knowing the performance specifications and limits of each MCP module eases the design modeling and problem resolution process by providing designers with known boundary conditions for each function, as opposed to dealing with multiple individual components that do not necessarily behave in fully predictable ways when integrated into a complete function. The MCP designer and producer resolve these issues before the product designer ever faces them.

Cost reduction remains the ultimate measure of value for any design approach, and MCPs may positively impact cost in several ways. The most obvious impact comes at the PWB level where MCPs focus the highest density interconnect structures only where needed, in the module substrate. This results in integrated MCPs with larger pitch than that possible with individually packaged integrated circuits (IC) directly on the PWB. These simplified PWBs cost less and generally result in higher assembly yields. Additionally, because module procurement results in essentially “known good functions,” PWB assembly yields increase even further by eliminating defective interactions between individual IC components. This also improves final product reliability since most infant failures and marginal performance interactions (among components) disappear.

Additional cost impact comes from supply chain management. Total electronics manufacturer supply chain management includes costs associated with creating and managing a part number in the manufacturing resource planning (MRP) system, device qualification, coordination and management, procurement management, and several other related factors.

Expanding MCP Demands

Today, several silicon vendors offer successful products with two chips together in a single package. The most common implementation, shown in Figure 1, consists of die stacking with one chip on top of the other. The most common product using die stacking techniques, a flash memory and a low-power SRAM packaged together, supports the handset and PDA markets. Generally supplied by different silicon vendors, the flash and SRAM chips incorporated into an MCP yield a product marketed by the flash manufacturer, largely due to reluctance to release confidential flash test vectors to another vendor.

As the demand for more sophisticated package integration continues to increase, the incorporation of logic devices drives further MCP innovation. For example, one solution places a device that requires memory to operate, such as a digital signal processor (DSP) or other microprocessor, in a package with its required memory. This not only saves space, but also reduces system complexity by integrating the memory interface into the package. The resulting I/O reduction allows a less complex system board and may eliminate routing layers and blind vias, providing lower system cost. Improved subsystem performance, a common side benefit, alone rarely provides significant motivation for choosing MCPs over conventional packaging.

Figure 2. Yield implications of placing multiple chips in one package.
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Business and Logistics Issues

As previously mentioned, several package solutions available today provide a sound technical approach to combining multiple chips into a single package. However, widespread adoption of these solutions generally remains limited to two and three chip memory-only MCPs. Attempts to integrate more chips, and more complex chip sets, shifts the focus to the business and logistics challenges associated with today's solutions. These challenges include product accountability, test logistics, intellectual property ownership and management, value capture, and market identity. To summarize, three fundamental issues impede the adoption of today's MCP solutions.

Multiple silicon vendor issues. Placing chips from more than one silicon vendor into a single integrated package introduces several interesting business challenges. An OEM design requiring an MCP incorporating chips from multiple silicon vendors demands a business relationship among these silicon vendors, allowing packaging of their chips with the chips from other suppliers. These business relationships remain difficult to establish, and must address and manage issues of accountability and confidentiality. When several silicon vendors provide chips for an MCP, who is responsible for overall MCP component quality? Who takes responsibility for issue resolution regarding defective devices? With multiple silicon suppliers' die in a single MCP, confidential test vector availability requirements for the supplier taking final responsibility for the integrated product often stops negotiations before they get started. Many silicon vendors consider their final test vectors proprietary and release them to no one for any reason.

Test and burn-in issues. Full test and burn-in at the package level addresses the accountability issue in today's common single-chip packages, as well as providing the silicon supplier with complete control over test methods, programs and vectors, an important component of the intellectual property associated with both memory and logic devices. Placing multiple chips into a single integrated package creates several problems because full test and burn-in of bare chips prior to packaging continues to present significant technical and cost barriers. Current MCP solutions generally require full test and burn-in after final package assembly, meaning that all silicon vendors with chips in the package must provide their test vectors to ensure final product quality.

For example, DRAM devices, which continue to grow in demand for handheld products, require a “burn-in” process following chip packaging to ensure device quality. Burn-in at the individual chip or wafer level remains both expensive and difficult, especially for high-volume memory devices.

Yield issues. MCP assemblers generally rely on silicon supplier's known good die (KGD) programs to assure the ultimate quality and yield of their MCP components. KGD programs, while somewhat common today, entail costs such as tighter engineering margins, longer test times on more expensive wafer test equipment and compounded yield losses at the module assembly level. Additionally, KGD programs frequently do not apply to leading-edge IC processes or chip designs.

Even with KGD and other testing methods, complete die testing before packaging remains difficult if not impossible with today's solutions. Die yield impact on MCP may increase costs as a result of compounding yields as the number of chips placed in a single package grows.

In addition to die yield, some fallout inevitably occurs during die handling and packaging, which leads to even more expensive yield losses where some good die end up in scrap because of being packaged with damaged die. Compound yield losses increase quickly as die counts in a single package grow, directly translating to higher product costs when die or package integrity cannot be fully ensured. Figure 2 shows how MCP yield rapidly degrades with increasing die count, considering variations in die quality/yield.

Current MCP solutions do not resolve these issues since they still rely on KGD technologies as well as highly sensitive processes and assembly techniques. Today's common MCPs also eliminate the possibility of any rework, further constraining their application to low chip counts and low-value MCP applications. The barrier for implementing any high-value chip into these packages remains high because of the risk of discarding the high-value chip as a result of one of the lower cost chips being found damaged or defective following assembly into the chip stack.

Figure 3. µZ Fold-Over logic and memory package stack.
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Emerging Technology

Emerging MCP technologies must overcome not only the technical hurdles of placing many die in a package, but also must resolve fundamental business, logistics and system cost issues. This applies to the entire supply chain, which includes OEMs, contract electronics manufacturers and semiconductor manufacturers. MCPs must move beyond the current achievement of many chips in a small footprint and profile by adding practicality. The emerging solutions also must offer testing flexibility, procurement versatility and assembly adaptability.

Today's MCP products typically place die on top of each other in an integrated package known as die stacking. While this generally provides the lowest package cost solution, it can create the business, logistics and system cost problems previously described as die counts and complexities increase. Emerging solutions overcome many of these hurdles by using a concept called “package stacking” that provides the ability to perform package-level test and burn-in of either individual die or selected groups of die before final MCP package assembly. An added benefit of some solutions allows sourcing the individually packaged die from multiple suppliers, allowing packages to join at the point of board-level assembly. An electronics manufacturer may procure standard memory separately from logic to meet various OEM memory configuration demands. As an example, the µZ Fold-Over package-stacking solution* (Figure 3) allows logic and memory to be individually sourced, tested and burned-in. Other emerging technologies offering similar features also may become preferred solutions by yielding practical, cost-effective and low risk MCPs with rapid time-to-market.


Until recently, MCP technology advances often waited for applications, not because of technical limitations but rather as a result of business and logistics barriers to chip acquisition. New and emerging packaging technologies offer innovative solutions to these nontechnical obstacles by allowing semiconductor suppliers to retain control of their yield data, test vectors and other intellectual property, as well as capture the value added by their components in the microelectronics supply chain. Yet these solutions also provide OEMs with the cost, size (both volume and area) and performance advantages available through MCP technology. Only the selection of preferred alternatives and rate of adoption remains in question.

*µZ Fold-Over package is a registered trademark of Tessera Technologies Inc.

Charles E. Bauer, Ph.D., senior managing director, may be contacted at TechLead Corp., 2192 Augusta Dr., Evergreen, CO 80439; (303) 674-8202; E-mail: [email protected]. John Riley, VP of Business Development, may be contacted at Tessera Technologies Inc., 3099 Orchard Dr., San Jose, CA 95134; (972) 233-9340; E-mail: [email protected].


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