By: Kay Lederer, Infineon Technologies SC300, Dresden, Germany
Barry Saville, Ingrid Peterson, KLA-Tencor, San Jose, California
As the semiconductor industry continues to push toward the 90nm node, controlling defect density in the lithography cell becomes ever more critical to the success of the overall manufacturing process. Thinner resists, new resist chemistries, tighter design rules and process windows, as well as shorter product life cycles, have placed greater demands on achieving and maintaining low defect densities.
Establishing new defect management methodologies that can achieve low defect densities has quickly become as important as critical dimension (CD) and overlay metrology in the development and implementation of new lithography processes.
In recent work at Infineon Technologies SC300, we conducted defect detection experiments on 300mm Czochralski (Cz) wafers using the following conditions: exposure by scanners, a single puddle-develop process with 2.38% TMAH containing surfactant, defect inspection on a KLA-Tencor 2351 series high-resolution imaging inspection tool, and defect review on an inspection tilt scanning electron microscope (SEM).
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