Cover Story: Bare Chip Stacking

Process Issues for Achieving High Density and Performance


Throughout the electronics industry, it is always desirable and sometimes imperative to improve circuit packaging density. This is particularly true in the areas of avionic and satellite electronic packaging. It has long been recognized that 3-D circuit packaging in the form of stacked devices can provide the greatest improvement in packaging. Unfortunately, the physical designs and performance requirements of most chips are not conducive to stacking. Examples of these limitations are:

  • The problem of escaping I/O from stacked die identical in size and I/O assignment.
  • When I/O have been wired out to the edges of stacked chips, they then must be wired down the side of the stack to the next level of interconnect.
  • Almost all chips only have one active surface and, hence, one avenue of wiring escape.
  • The active surface of most chips has little or no passivation protection, and most nitride/oxide barrier levels are fragile. This means there is a significant chance of damage to the chip during the stacking process.

The approach described in this article can be applied to devices at the wafer or chip level and requires no additional processing to the devices at any level prior to preparation and actual stacking.

Design and Materials

Certain areas in the electronics industry often require unique packaging solutions. However, their demanding requirements in terms of density, reliability and performance can yield enabling technologies that provide great benefit throughout the electronics industry. Likewise, adaptation of standard electronics packaging technologies to these specialized applications can later lead to enhancements that benefit the industry as a whole. This has proven to be especially true in the stacking of bare die with no unique preprocessing requirements.

Figure 1. Cross sectional view of the typical bare die stack using a combination of flip chip and wire bond devices.
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A key element of die stacking is the insertion of a standoff between dice (Figure 1) to provide clearance for wire bonds when applicable. The standoff should be of the same material or at least have the same coefficient of thermal expansion (CTE) as the bulk material of the devices. The adhesive bonding the standoff to the surface of the bottom die should be a compliant material that allows for expansion mismatch over time and temperature. The material should maintain its compliancy over the product's life. Polyimide or high-grade silicone are examples of such adhesives. The second die then can be bonded onto the standoff.

Although removing and replacing defective die from a multichip module (MCM) is never an attractive proposition, it is recommended that the second die and any subsequent die be bonded with a reworkable adhesive such as a thermoplastic. Filled adhesive between the standoff and the backside of the die improve thermal conductivity in the stack.

Most chip stacking solutions require additional processing of the chip at the wafer level prior to dicing. Special wafer-level processing implies involved handling of a small quantity of wafers and an inefficient allocation of resources. These types of processes typically do not lend themselves to the efficiency of most high-volume silicon foundries. Examples of previously used stacking solutions include:

  • Back-to-back chip stacking. This involves placing a wire bond chip face up onto the back of a previously mounted flip chip. This is effective for two chips and requires additional wafer-level processing to the devices going on the bottom of this two-high stack.
  • Chip cubing. This method applies a transfer layer to the chips at the wafer level that brings I/O out the edge of the chip. While this method can provide great density, it is very involved and often not cost-effective.
  • Wire bond chip on top of wire bond chip. This approach also has proven effective and requires no wafer-level preprocessing. The main limitation of this approach is that the top die must be small enough to allow adequate access to the wire bond pads of the bottom die.

Surface Preparation

Critical to the success of chip stacking is the protection of the active surface of the base chip. Many devices have a protective passivation layer applied to the surface of the die. This layer generally is a compliant, organic material that provides physical and environmental protection. However, many devices, particularly those used in cost-driven commercial applications, do not have a final passivation layer applied to them. Instead, these devices have only the exposed termination layer on the top surface. This material will be a glass (e.g., silicon dioxide or silicon nitride) with a high fragility level (Figure 2). As a result of the metal circuits on the layers beneath it, the termination layer will have a textured surface with exposed peaks of brittle material, all of which make this layer very prone to mechanical damage if not properly protected. Any physical contact with such a layer can result in surface trauma and device failure. A passivation layer must be applied to the surface of the device to ensure devices can withstand assembly operations.

Figure 2. Cross section of a silicon device without passivation near its surface.
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Wafer- and Chip-level Preprocessing

A method can be devised to apply a passivation coating to the surface of a device that provides physical and environmental protection while leaving clearance for wire bond connection. Using an adhesive/encapsulant auto dispenser, a layer of encapsulant such as polyimide can be deposited onto the active surface of the device and the material then cured to provide a robust protective layer. Once a step-and-repeat deposition pattern has been developed, the most efficient way to deposit such a coating is at the wafer level. The coating can also be applied at the device level.

If devices are procured at the wafer level, it also is advantageous to thin the wafers. This further enhances density and increases the manufacturability of some facets of assembly, such as wire bonding. Die thinning to 100 µm is not uncommon, although thinning to 300 to 400 µm provides benefit while minimizing handling challenges.

Die Stacking with Reworkability

Once the active surfaces of the devices have been processed, including coating if necessary, they may be placed in the package and stacked per a typical process flow. As stated above, the adhesive needs to be compliant and may even be a form of the coating material initially applied to the die surface. Using thermoplastic materials allows for die to be removed and replaced during stacking. Material application must be done in a way that allows for complete curing and venting of any volatiles while resulting in a high reliability bond (Figure 3).

Figure 3. A total of four stacked wire bond devices.
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There is no theoretical limit as to how high die can be stacked in the manner described. Limitations come in the form of practical considerations such as processing precision, individual die yields, and thermal and electrical performance requirements. However, die stacking can be further enhanced by first placing a flip chip die and then placing additional wire bond die on the back of it. This approach is most effective when a logic device with high I/O is placed on the bottom of the stack in the flip chip position, and a supporting memory die is above it. Additionally, double-sided packaging can be developed that allows chip stacks to be placed on both sides of the package, again doubling the density.

Die stacking especially lends itself to devices whose I/O can be brought off the stack together, with just a few I/O brought off separately. An example of this would be memory devices configured in a relatively narrow bandwidth, such as X8 or X16. This approach simplifies connectivity while optimizing density. The flip chip/wire bond stack can be highly effective for either similar die with I/O that can be “commoned,” or with a higher I/O device in the bottom flip chip position and support devices higher in the stack.

Electrical Performance Considerations

A key design consideration in any device stacking configuration is electrical performance. In terms of electrical performance, stacking and package parasitics in the form of resistance, inductance and capacitance (R, I, C) affect signal delay, noise and simultaneous signal switching limits. In most stacking geometries, package effects do not begin to have much impact on signal delay until clock speeds approach 100 MHz. In bare die packaging, most delay is found in the capacitance loading on signal and power planes. Noise can be managed by providing ground shielding for noise-sensitive signals and by matching impedances across package/stack interfaces, such as those between stack circuitry and wire bonds. Limitations in simultaneous switching are related to delay and noise because they are due to large voltage spikes when a large number of on-chip signal drivers switch at the same time. This is caused by the sharp di/dt change across the package, which is caused by a large number of signal drivers switching at once. This creates a sharp noise pulse and causes a voltage drop in the power supply. These effects can be managed by providing ample power inputs interspersed among the signal I/O likely to be switching simultaneously.

Most of the electrical effects causing performance degradation relate more to the packaging containing the stacks than the stack themselves. Stacking die offers the benefit of minimizing package dimensions, allowing for shorter signal traces and simpler power plane geometries.

Quality and reliability are critical to the success of any packaging technology, but this is especially true of applications with extreme environmental conditions such as automotive and satellite electronics. Such applications often can benefit most from the density achieved through die stacking. Reliability is equally important for a widely used commercial application with an extremely large population of units in the field.

For these reasons, a broad range of accelerated life tests and qualifications have been performed on typical versions of stacked modules. Critical tests include extended temperature cycling to verify the thermal expansion matching of the basic elements of the stack and the compliancy of the bonding agents. A properly designed and assembled module containing stacked bare die can provide reliability comparable to any single device module.


Stacking of bare chips offers a new level of packaging density and performance while requiring levels of processing well within the capabilities of most electronics assembly facilities. The level to which this form of stacking can be instituted can be made commensurate with the level of integration required. Process development and product show this approach to be a viable and reliable solution to continuing electronics integration.

Keith Sturcken, Sheila Konecke and Kent Mason may be contacted at BAE Systems, Manassas, VA; (703) 367-4948; Fax: (703) 367-3540; E-mail: [email protected], [email protected] and [email protected].


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