In The News

MEMS 2003 in Review

By Joe Brown, Suss MicroTec

KYOTO, JAPAN— The 16th Annual International Conference on Microelectromechanical Systems (MEMS), sponsored by IEEE and the Robotics and Automation Society was held at the Kyoto International Conference Hall in Kyoto, Japan from January 19 to 23, 2003.

A record number of 500 abstracts were received, with 173 accepted for presentation. With 526 participants from 25 international regions, the event featured invited talks on each full-day agenda, followed by technical and poster sessions.

This year, packaging for MEMS applications was acknowledged as the foremost area of need. Clearly spelled out in his invited talk, Sean Neylon, CEO of Colibrys SA, Switzerland, stated, “Timing is absolutely critical.” Neylon, presenting “Business Models for the Successful Commercialization of Silicon-based MEMS,” added, “Packaging is ultimately linked to the ability to provide effective solutions.”

In his invited talk “Nanotechnology for the Future MEMS,” Tomoji Kawai, Osaka University, Japan, provided a look into the future as he explained the continuous need for miniaturization in technology. Information storage, heading to the atomic size, was presented as one of several technologies to demonstrate the trend to nanoscale.

In his presentation, Dana Anderson from the University of Colorado presented a scientific approach, whereby lasers are used to cool and slow the speed of atoms. Comparing atoms and photons, he used a common laser pointer as an example where the light-emitting photons could be replaced with atoms. He called on the MEMS community to continue efforts to reduce bulky systems with state-of-the-art MEMS-based systems in science and technology.

MEMS, with needed support from novel packaging concepts, will continue advancing from R&D to commercial offerings that will have some impact on our everyday lives.

TI's Logic Devices Now Lead-free

DALLAS — As a leading supplier of lead-free electronic integrated circuit (IC) packages, Texas Instruments (TI) announced that its complete logic portfolio now is available in lead-free solutions. By implementing load-free strategic finishes and balls, TI logic packages are classified per the J-STD-020B (maximum reflow temperature of 250°C) lead-free parameters.

Lead Frame Packages. TI has chosen the nickel/palladium/gold (Ni/Pd/Au) finish as the preferred lead-free finish for all lead frame-based packages. Two major customer concerns driving the decision to use the Ni/Pd/Au finish were compatibility with lead-free solders and tin whisker growth.

Ball Grid Array (BGA) Packages. TI also has qualified lead-free ball alloys for its LFBGA, VFBGA and WCSP logic packaging offerings. The MicroStar BGA, MicroStar Jr. BGA and NanoFree Logic packages all use Sn/Ag/Cu alloys. Sn/Ag/Cu alloys are the lead-free choice in the industry for BGA packages.

Moisture sensitivity performance of all IC packages is a concern because of the potential for “popcorning” and delamination caused by moisture expansion trapped in the plastic during reflow. The higher melting point of lead-free Sn/Ag/Cu solder alloys compared to Sn/Pb demands higher peak reflow temperatures in lead-free soldering processes.

All TI Logic Products lead frame packages are available in the Ni/Pd/Au finish and rated for use in lead-free processes per J-STD-020B. Other lead-free options can be supplied upon demand for packages scheduled for conversion to Ni/Pd/Au finish by 2Q 2003. Logic devices using array-style packages currently are available with the Sn/Ag/Cu ball alloys and also are rated per J-STD-020B parameters.

MEPTEC RF Symposium

By Julia Goldstein

There has been a lot of talk about the need for front-end and back-end manufacturers, along with equipment suppliers and material vendors, to work together to provide the best final product. Perhaps nowhere is this need more apparent than in radio frequency (RF) technology, where RF designers and packaging engineers often seem to speak different languages. MEPTEC's one-day symposium on Packaging, Assembly and Testing in radio frequency (RF) Technology brought together professionals from various backgrounds to discuss the current state of wireless technology and make predictions for the future.

Several speakers prefaced their talks by informing the audience that they were from the RF, not the packaging, world. As IEEE Fellow George Vendelin said, “The RF industry has a terminology all of its own,” one with which many of us coming from the packaging side have little familiarity.

Operating frequency is a key issue for the impact of RF technology on packaging, but there is much more to understanding RF requirements, as Michael Gaynor (Amkor) made clear in his talk on System-in-Package (SiP) solutions for RF. An RF SiP is “not just a package anymore” and can include, for example, electromagnetic shielding, a feature previously implemented at the product level, adding more complexity to package design. A variety of filters can be embedded in substrates, eliminating costly components but making footprint reduction more difficult.

Keynote speaker Stephen Pawlowski (Intel) discussed the goal of integrating RF passive components, analog front end and digital baseband functions into a single CMOS chip radio. With current technology, separate radios are needed to support each of standards being used (see sidebar), and these radios are often packaged into a single module. RF designers are working on combination chips that can function in more than one mode and therefore be compatible with 802.11a, b and g. Several obstacles need to be overcome, both in circuit design and in packaging, to achieve complete integration in a cost-effective manner, and Intel admits that success is not guaranteed. Pawlowski mentioned that comments like “SOC is dead” really mean that it is not currently cost-effective — if analog and digital functions are to be combined on a single chip, the ability to test the analog circuitry separately can be important to avoid throwing away a good chipset because of problems on the analog side. RF designers are really pushing for SOC (system on chip) as the future of RF while companies like Tessera and Amkor are talking about multi-chip SiP solutions that work with today's chipsets.

Understanding the Alphabet Soup of RF Standards

Here is a brief synopsis of IEEE RF standards for those of us in the packaging industry that may never have heard of 802.11. According to Webopedia (, “802.11 refers to a family of specifications developed by the IEEE for wireless Local Area Network (WLAN) technology. 802.11 specifies an over-the-air interface between a wireless client and a base station or between two wireless clients.” The 802.11 specification has developed into several different protocols since the IEEE first adopted it in 1997, operating at different frequencies, data rates and transmission modes. Most wireless LANs today comply with the 802.11b standard, operating at 2.4 GHz with data rates up to 11 Mbps. 802.11a operates at 5GHz to avoid interference within the crowded 2.4GHz band (Bluetooth radios and cellular phones, some cordless phones and microwave ovens all operate at 2.4 GHz) and specifies data rates up to 54 Mbps. 802.11a offers superior performance but shorter operating range than 802.11b. Because of the different frequency ranges, radios using 802.11a cannot communicate with 802.11b devices, and vice-versa. To further complicate things, IEEE is introducing 802.11g, which operates at 2.4 GHz but uses higher data rates than 802.11b.

More information is available on the Web at

SEMI Reports 4Q 2002 Silicon Wafer Area Shipments

SAN JOSE, CALIF. — Worldwide silicon wafer area shipments have increased by 19 percent in 2002 compared to 2001 area shipments according to Semiconductor Equipment and Materials International (SEMI) in its quarterly analysis of the silicon wafer industry. Revenues, however, grew by only 6 percent compared to 2001 numbers.

Silicon wafer area shipments in 2002 totaled 4,681 million sq in (MSI), up from the 3,940 MSI shipped during 2001. Revenues increased to $5.5 billion from the $5.2 billion posted in 2001. Fourth quarter silicon area shipments declined 10 percent from the prior quarter, but were more than 29 percent higher than the fourth quarter of 2001.

Stanley Myers, president and CEO of SEMI, said, “We are pleased with the area shipment improvement in 2002. However, the lower revenue growth indicates that the silicon manufacturers will continue to face difficult decisions regarding technology and capacity investments, especially as fabs ramp up with advanced design rules.”

IMAPS Emerging Technologies

WASHINGTON, D.C. — The International Microelectronics and Packaging Society (IMAPS) announces the first book in the IMAPS Series on Emerging Technologies. Foldable Flex and Thermal Silicon Chip Packaging Technology, edited by John. W. (Jack) Balde, Ph.D., has been published recently by Kluwer Academic Publications.

Jerry Sergent, chair of the IMAPS Book Subcommittee, states in his review that this new publication covers a leading edge technology that is both timely and in-depth. Additionally, he recommends this book for those involved in the electronics packaging industry. “The foldable flex and thinned chip technology is new and gives packaging engineers and opportunity to learn a great deal about a technology that is still developing,” he added.

Contact IMAPS at (202) 548-4001 or visit and click “Hot off the Press.”

Universal Opens Facility

SHEKOU, GUANGDONG PROVINCE, CHINA — Universal Instruments Corp., a leading global supplier of electronics and semiconductor manufacturing equipment, opened a world-class manufacturing facility here at the end of February.

The new 4,700 sq m facility in located in China's southern province and is the foundation of the corporation's new global growth strategy.



By Julia Goldstein

SAN JOSE, CALIF. — LSI Logic gave an update on their flip chip and wire bond BGA efforts during MEPTEC's monthly luncheon in February. Speaker Ivor Barber described stress modeling for Cu/low K technologies with a variety of different underfill materials and showed how interfacial stress changes during manufacturing. Correct choice of underfill is crucial for Cu/low K packages to avoid delamination problems, which are not an issue with conventional substrates. LSI Logic's “next generation flip chip” is a 10-layer package that allows for flexible signal I/O placement capability without moving the BGA bumps. De-coupling capacitors can be placed within the package, but there is some argument over whether this is the best approach. For low-frequency applications in which flip chip is not required, Barber presented a wire bond BGA with an effective staggered pad pitch down to 27 µm. Standard Au wire is used, with short wires to connect power and ground and longer wires for signal lines. An integrated heat spreader can provide thermal performance comparable with that of flip chip designs.


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