Development Packaging Solutions: Flip Chip and Beyond

By Ilya Grigorov

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In times of reduced research and development (R&D) budgets and a slump in venture financing, time- and cost-efficient execution of the new product development often is a matter of survival. Yet, few developments follow a straightforward path, and this can be particularly true for products requiring advanced packaging.

For product designers, migration to advanced packaging often implies venturing into an area beyond immediate expertise and experience. The larger players can meet this challenge by having a broad selection of experts, established manufacturing operations, and time-tested logistical support. The medium-sized and smaller companies, lacking such internal resources, can have a harder time coping. Even when the original design is well suited for manufacturing, the inevitable fine-tuning often introduces incompatible and costly elements. Performed without care, these late additions may render the final design totally unmanufacturable.

A good risk mitigation technique to handle such late changes includes selection of core technologies that are sufficiently flexible with respect to a change in the assembly sequence, extended in-process temperature range and imperfect incoming material. The adaptability to the changing procurement chain also factors prominently since a bill of materials is likely to change multiple times before development is complete.

Yet often, in a rush to conform to the perceived “industry standards,” these factors are not given proper consideration. An example can be found in solder bump flip chip assembly, a default standard among American companies. The limitations of this type of flip chip are well documented: loose pitch (150 µm and up), wafer-level processing with a potential for significant up-front costs, and incompatibility with common substrate materials. An early commitment to this technology may have significant cost and schedule ramifications if the die or substrate designs have to be changed. Alternatively, the designers can forgo the benefits of the flip chip technology and stick with the more conventional packaging approaches, leading to a compromise in the product performance.

Stud-bump Flip Chip

In 1998, when Teledyne Microelectronic Technologies made a commitment to provide access to flip chip technology, it became apparent that the technological and logistical diversity of the customer requirements in the specialty electronics business made the sole commitment to solder bump flip chip attachment highly impractical, in spite of the existing infrastructure's benefits.

The decision was made to invest the capital and R&D resources toward adopting stud-bump-based flip chip-attach technology. The basis of the die interconnect is a stud bump, i.e., a truncated ball of a ball bond that can be deposited on the original Al pads of the die using a conventional wire bonder. Intrinsically, this process does not require the die to be supplied in wafer form. The die can be probed and inked without upsetting the process. The stud-bumped die can be attached to the substrate by various techniques: gold-to-gold bonding (ultrasonic and thermocompression), conductive epoxy or via pressure contact maintained by a nonconductive epoxy. It even can be soldered to the substrate using gold-compatible solder, such as Au/Sn or In/Pb. In short, the technology provided the critical benefit of adaptability: it was compatible with a wide variety of substrate materials and it could be implemented over a wide range of temperatures.

The intrinsic adaptability of the stud-bump flip chip can be fully exploited only if the right set of equipment is chosen. For stud bumping, Teledyne selected a Delvotec thermosonic gold-ball bounder with linear Z-motion, and the wire bonder was tuned for higher control over the bump shape rather than speed. Using 25 µm Au/Pd wire, ball sizes down to 55 ±2.5 µm have been achieved in production mode, and the process maintains the thickness of the ball within 3 µm of the designated target. The wire bonder is programmed for an additional jigging motion, designed to shear the wire at the specified height from the surface of the ball.

The flip chip attachment is performed on Panasonic FCB-II machines equipped with time/pressure and ultrasonic heads, in-situ dispenser and epoxy/flux transfer station. The bonder accepts die in dry- and gel-packs, as well as in tape frames. The software is highly modular, allowing for different die to be supplied in different formats and the same die to be bonded to different substrates with minor reprogramming.

The combination of these two highly flexible machines has enabled a number of different processes to be developed and introduced into manufacturing. The tightest pitch achieved in production was 80 µm for stud-bumped die and thermocompression bonding to a 25 µm line/space thick film substrate.

The initial bet on the most versatile technology decreased the risk for customers in the initial stages of designing flip chip assembly into their products. In a matter of hours and days, as opposed to weeks and months, those designs were tested in terms of effective throughput of the assembly technique, compatibility with the upstream and downstream processing, and adaptability to the supply chain. As an example, when stud-bumping of small GaAs die appeared impractical due to the difficulties in obtaining the wafers from the foundry, a silicon interposer wafer was bumped instead and a thermocompression bonding process was developed and characterized. Similarly, when poor planarity of a customer-furnished ceramic substrate prevented the use of an ultrasonic-attach process, a more forgiving conductive epoxy technique was successfully used. In both cases, the designers were able to receive the time-critical prototypes despite running into an unfavorable reality check. Providing extensive feedback within a compressed timeframe was made possible with a new business paradigm, called rapid product development (RPD).

RPD Paradigm

The RPD paradigm calls for the engagement of the OEMs at the earliest design stage, integrating into the OEM's development cycle, and assisting that development with the objective of a seamless transition from prototypes to production. The basic operational principles used are:

1. Early customer analysis of the assembly steps for critical manufacturing requirements and logistical support.

2. Development of risk mitigation strategies to offset potential roadblocks.

3. Prototyping on equipment and tooling identical (or scaleable) to volume manufacturing with a predefined throughput.

4. Minimum documentation sufficient to maintain configuration control.

The implementation of this paradigm allows the outsourcing OEMs to have the level of design, manufacturing, and test support identical to the one expected within the organization. Thus, the paradigm is a significant departure from the way that CMs tend to interact with their OEM counterparts.

Ilya Grigorov, Ph.D., senior technical staff member, may be contacted at Teledyne Microelectronic Technologies, 12964 Panama St., Los Angeles, CA 90066; (310) 577-3895; Fax: (310) 574-2080; E-mail: [email protected].


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