Toshiba develops embedded DRAM for SOI wafers

June 13, 2003 – Toshiba Corp. says it has developed new memory cell technology that will let chipmakers build DRAM system-on-chip (SOC) devices on silicon-on-insulator (SOI) substrates, which will help reduce power consumption and increase chip efficiency.

Toshiba plans to mass-produce these devices for broadband network applications by 2006.

The new memory cell technology, a 96Kbit cell array dubbed floating body cell (FBC), eliminates the necessity of capacitors where current DRAM cell stores data. It achieved successful operation in all bits, a 36-nanosecond access time, 30-nanosecond data switching time, and 500-millisecond data retention time (at 85 degrees C). The technology will be used for embedded DRAM system LSI for the 45-nanometer generation on.


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