UMC takes wraps off new strained silicon process

June 12, 2003 – UMC, Taipei, Taiwan, has unveiled new strained silicon technology using wafers built on substrate technology from AmberWave Systems, Salem, NH.

The process aims to enhance CMOS performance with over 20% current driving capability on a 70nm strained silicon transistor, with a speed enhancement of over 10% on a test circuit. The results were presented at the 2003 VLSI symposium in Japan.

S.W. Sun, UMC VP of central research and development, said the company is also working with AmberWave to enhance p-channel transistor performance, improve strained layer defect density, and decrease substrate costs.


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