By Kurt Christenson, FSI International, Chaska, Minnesota

The deposition of blanket films with a subsequent etch after gate patterning remains the leading candidate for integrating high-k gate dielectrics at the 70nm node. Early high-k material candidates such as BST etched easily in a range of acidic chemistries, but device and materials studies have now converged on the oxides, nitrides, and silicates of Al, Zr, and Hf, and particularly on HfO₂ based compounds [1].

Removal of the high-k material from the source and drain regions is required after gate patterning. This removal must be done selectively to the polysilicon gate electrode, to the underlying silicon, to silicon nitride spacers, and to deposited silicon oxide used for shallow trench isolation and spacers. Typical high-k:SiO₂ etch selectivity specifications range from 1:1-5:1. Etch rates of 0.5nm/min for batch and 5nm/min for single-wafer processes are desired. The traditional plasma and wet etch chemistries used in the formation of SiO₂ /polysilicon gates have thus far been unable to provide the necessary selectivity and etch rate.

Given the numerous integration issues surrounding high-k gate dielectrics, and the differing needs of the high-performance and low-power devices, the industry may choose to implement a variety of integration schemes simultaneously. For instance, the more easily etched compounds of Hf and Zr with Si, O, and N may be chosen initially as transition materials, similar to the role of FSG in the evolution to low-k, with pure HfO₂ or other materials used in later nodes if needed.