JULY 2–SAGAMIHARA, Japan–The Japanese government and the semiconductor industry has funded a research center that will open a 300-mm wafer line here to test and develop specifications for 90-nanometer and smaller process technologies.
The Advanced SoC Research & Development Center was founded so chip makers can share increasing research and development costs for deep-submicron process technologies, which are becoming increasingly difficult for fabs to shoulder alone.
The center has a 48,000-square-foot ISO Class 3 cleanroom with a pilot line for 90-nm processes. The cleanroom, which has a cleanliness level below that of conventional fab-is equipped with i-line, KrF and ArF lithography systems. Construction was financed with about $265 million from the secondary supplementary national budget in fiscal 2001.
Researchers will hammer out standard specifications for 90-nm processes and masks.
The unified 90-nm process will be defined by five major supporters of the center-Fujitsu, Matsushita, NEC, Renesas and Toshiba-based mainly on technologies provided by NEC. This year’s research agenda also includes the development of 90-nm deliberative devices that realize ultralow-voltage operation; the verification and expansion of libraries and intellectual property; and the start of a 300-mm wafer shuttle service in October.
The pilot line will serve as a platform for joint R&D into noncompetitive areas of process technology, providing member companies with development efficiencies while allowing each to introduce its own differentiating technologies.
The National Institute of Advanced Industrial Science and Technology, an independent public R&D organization, is sending 10 researchers to the center to join about 100 engineers from the Advanced SoC Platform Corp. (ASPLA), an industry group funded by supporters of the center.
For 2004, the researchers plan to transfer the wafer process developed at the center to mass-production fabrication facilities and to begin developing the 65-nm process