Productivity Enhancements in Advanced Packaging Lithography

Controlling electroplating contact zones and high illumination


The need for faster devices and smaller form factor has resulted in a prolific adoption of advanced packaging techniques. As semiconductor devices continue to migrate to smaller features, higher frequencies, higher power densities and lower voltages, the industry requires an aggressive packaging technology roadmap. Otherwise, packaging will become the limiting factor in the continued evolution of semiconductor technology. End-user applications requiring more complex and functional forms of device packaging continue to increase at a rapid pace. Foremost among these advanced packaging techniques is the use of wafer bumping and wafer-level chip scale packaging (WLCSP). Because of the complex nature of these packaging applications, front-end manufacturing techniques for photolithography have been widely adopted. The dramatic increase in chip density and input/output (I/O) as well as the introduction of multi-layer I/O redistribution requirements have resulted in the adoption of 1X stepper lithography as a method of image transfer for these applications.

This article examines the productivity enhancements introduced to address future requirements for advanced packaging. The first enhancement has been developed to control the electroplating contact zones at the edge of wafers for both positive and negative photoresist. The second uses a high-intensity illumination system for higher system throughput with ultra-thick photoresist films.

Market Growth

Recent advances in substrate technology and material support have eliminated significant bottlenecks that historically hindered the wide adoption of flip chip technology. Despite a global recession in the electronics industry over the last few years, demand for flip chip interconnect is growing. The key drivers in flip chip use are performance considerations, on-chip power distribution and form factor needs. In addition, high-performance logic suppliers such as ASIC, field programmable gate array and microprocessor manufacturers continue to expand their use of flip chip in package (FCIP).

Figure 1: The demand for flip chip interconnect is growing.
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Figure 2: WLCSP is experiencing a compound annual growth rate of 43 percent.
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The solder bump flip chip demand can be divided into two categories: flip chip on board (FCOB) and FCIP. FCOB demand includes applications such as watch modules, pagers, disk drives and preamplifiers, etc. FCIP applications include consumer products, telecommunications infrastructure and wireless applications. Figure 1 illustrates the FCOB and FCIP demand over the next several years. In addition to flip chip, wafer-level chip scale packages (WLCSP) are also gaining acceptance. Wafer-level packages are formed on the die prior to the dicing process sequence. The result is a final package that is nearly the same size as the die. Singulation occurs only after the device is fully packaged. Figure 2 illustrates a compound annual growth rate (CAGR) of 43 percent in WLCSP demand.

It is challenging to predict the split between WLCSPs and flip chips over the next five years. Part of the difficulty results from the subtle and evolving characteristics used to differentiate these two packaging technologies. One differentiation between these two technologies is the pitch and solder ball size. Typically, WLCSPs involve 500 µm or greater pitches of area array connections, with solder ball dimensions of 150 µm or greater. Flip chip applications involve either peripheral or area array I/O, with pitches of 250 µm or less, with solder ball dimensions below 125 µm. In addition, flip chip devices typically require underfill material, while WLCSPs are expected to provide sufficient board-level reliability without the addition of any underfill material.

Technology Trends

The adoption of flip chip and WLCSP has resulted in several paradigm shifts. Electroplating technology is gaining widespread acceptance due to superior process performances. In addition, electroplating technology can also easily address future lead-free bumping requirements. Figure 3 illustrates a typical mushroom-plated solder bump. An ultra-thick photoresist allows sufficient solder volume buildup to eliminate the requirement for an umbrella above the thickness of the resist. In addition, there is also a trend towards straight-wall plating. The adoption of straight-wall plating techniques will require high aspect ratio performance at the lithography process step.

Figure 3: The structure of a typical mushroom-plated solder bump.
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While the lithography requirements for wafer bumping are subject to the same production and yield demands as front-end semiconductor fabrication, the considerations for back-end lithography are significantly different. Some of the unique requirements for advanced packaging lithography are discussed below.

Thick Resist Lithography. The process operating conditions for thick photoresists are considerably different than for thin photoresists. With thick films, the concerns are centered on aspect ratios, downstream plating performance and process latitudes. Ultra-thick photoresist also requires a large exposure dosage for high aspect ratio lithography.

The lithography projects an aerial image that can be focused at various depths within a thick photoresist film. This enables steeper sidewall angles and overall higher image quality, regardless of the photoresist type or thickness being used. This is especially critical for thick photoresists used in straight wall electroplating applications. Contact and proximity aligners have virtually no focus capabilities and imaging performance is further reduced in thick photoresist applications. In addition, it can be optimized for larger geometry while retaining both depth of focus (DOF) and large exposure fields. A low numerical aperture and broadband illumination spectrum is key for successful advanced packaging lithography.

Wafer Edge Processing Requirements. To ensure a seamless manufacturing process, wafers processed using stepper technology must be compatible with the next process sequence. After the photoresist is patterned, the wafer is processed for metal deposition. Certain metal deposition techniques such as electroplating require the outer edge of the wafer to be clear of any resist material. The use of positive resist materials requires the outer edge of the material to be exposed during the lithography step to ensure resist removal during the develop process, while the use of negative resist material requires the outer edge of the wafer to be protected during the lithography process sequence.

Process Yields. Yield is one of the primary factors affecting equipment selection for semiconductor manufacturers. Taking into account the various process sequences that have been conducted on a wafer prior to bumping, yield loss at the lithography step is not acceptable. A combination of reworkable and non-reworkable yield defects introduced by contact and proximity aligners can lead to a significant increase in overall cost. Using non-contact exposure techniques to form images eliminates yield losses associated with flood exposure techniques.

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Figure 4: A dual lamp illuminator and a 1,200 W lamp provide increased wafer plane irradiance.
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The wafer edge exposure requirement occurs when a positive photoresist material is used during device production. The incoming wafer is mounted on the prealigner and the outer edge of the wafer is exposed using a high-intensity lamp. The use of positive spin on resists leads to material buildup towards the outer edge of the wafer. The wafer edge exposure feature provides increased process improvement by allowing higher wafer plane intensity at the outer edge of the wafer.

Edge exclusion coverage is required for processing negative photoresist materials. This requirement is addressed using a mechanical ring that prevents the negative resist from being exposed, ensuring that the resist material washes away during the develop process.

The use of thick resists for advanced packaging applications has created unique process and equipment challenges. A 1,200 W lamp and a dual lamp illuminator design can provide increased wafer plane irradiance. The use of a 1,200 W lamp illuminator design provides increased wafer plane irradiance (≥ 2250mW/cm2), which results in an estimated 10 percent throughput improvement or die on the wafer layout. The dual lamp illuminator design (Figure 4) features the use of two 1,200 W exposure lamps and is designed for customers using thick resists with high exposure doses. The increased wafer plane irradiance (≥ 3400 mW/cm2) provides an estimated 30 percent throughput improvement at high exposure dose.


Flip chip technology is experiencing a new period of explosive growth. Traditional methods of lithography such as contact and proximity aligners are no longer adequate to address the technology demands in a cost-effective manner.


For a complete set of references, please contact the authors.

MANISH RANJAN, strategic marketing manager, SCOTT ZAFIROPOULO, director of strategic marketing, and WARREN FLACK, director of applications, may be contacted at Ultratech Stepper Inc., 3050 Zanker Road, San Jose, CA 95134; (408) 321-8835. E-mail: [email protected].


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