Tessera 3-D Symposium Demonstrates Greater Supply Chain Cooperation, Advanced Packaging Media Sponsor

Driven largely by the wireless handset market and emerging high-performance computing requirements, the semiconductor industry is increasingly looking to advanced packaging solutions as a means of achieving the reductions in package height, area and cost needed to sustain electronic product innovation. However, some key challenges associated with integration and industry-wide collaboration must also be addressed. These themes, along with some proposed solutions, emerged during Tessera Inc.’s 3-D Packaging Symposium at SEMICON West.

More than 100 technologists and executives attended the event, held at the Fairmont Hotel in San Jose. Experts from throughout the semiconductor supply chain &#8212 including chip manufacturing, packaging, materials, EMS and assembly leaders &#8212 covered topics ranging from the global outlook for 3-D packaging to focused discussions on materials, reliability, wireless integration and memory densification.

In his welcome and introduction, Tessera’s chairman and CEO, Bruce McWilliams, set the tone for the Symposium by examining the value proposition 3-D packaging technologies provide to the industry, namely increased miniaturization, performance and ultimately lower cost. To illustrate this point, he pointed out that the volume of functional silicon in one supercomputer rack takes up approximately 1 cubic centimeter of space &#8212 most of the rest of the floor-to-ceiling rack is comprised of various levels of packaging and interconnect. Advanced 3-D packaging technologies can not only dramatically reduce the size of electronic products ranging from super computers to cellular handsets, but also improve performance and lower cost. McWilliams noted that intensified cooperation throughout the supply chain is needed to realize 3-D package advantages, which can be applied to a broad range of consumer electronic products.

Keynote speaker Jan Vardaman, president of technology consulting firm TechSearch International, provided a global perspective on 3-D packaging applications. Driven in large part by wireless applications, the industry is shifting its focus to 3-D packages, which demand higher functionality in a small space, particularly in the case of mobile phones. Handset makers from around the world, including the U.S., Europe, Japan and China, are increasingly using both die stacking and package stacking to meet feature and size requirements. While broader adoption and resolution of cost issues depends on solving several key problems, such as addressing the known-good-die (KGD) problem and optimizing wafer/die-thinning technologies, Vardaman concluded that “3-D packaging has arrived.”

According to Catherine de Villeneuve, Tessera’s director of RF markets, wireless handsets, which are now integrating voice and data with more advanced features such as digital cameras, MP3 players, wireless gaming, GPS and other functions, accounted for 82 percent of multi-chip packages shipped in 2002. As was the case with CSPs, the cost-sensitive handset market is once again driving the need for advancement in packaging technology to accommodate added functionality in compact form factors. An area gaining increased attention involves optimizing the integration of passive functions at various levels, including chip, package and board.

A noteworthy trend in cell phone integration is the emergence of IC, package and radio module integration. For every new function incorporated into wireless handsets, said Glenn Raskin, a member of the technical staff of Motorola’s Wireless and Broadband Systems Group, the industry mantra should be: “integrate, optimize, eliminate” where possible. Following this process to determine where components, process steps, packaging area, etc., can be eliminated is key to optimizing miniaturization and functionality, at the lowest possible cost.

Mike Steidl, vice president of advanced product development at Amkor, pointed out that package stacking can now provide multi-sourcing flexibility and address the KGD problem by allowing individual devices to be tested prior to stacking. The die stacking approach, on the other hand, also provides important benefits, such as small size, low package profile, and low cost. The question of when to die-stack versus when to package-stack should be evaluated and modeled based on customer requirements. This sentiment was also expressed by Tessera’s Jeffrey Demmin, director of product marketing, who also noted that die stacking can be the solution of choice for high yielding devices available as bare die, whereas packaging stacking is the solution of choice when combining higher and lower yielding devices, or in a scenario where particular ICs require burn-in.

Stacked CSP Trends

Stacked CSP technology was cited as critical to the future of several device types, particularly accelerating the availability of next generation double-data-rate (DDR) DRAMs. Sunny Khang, technical marketing manager for Hynix Semiconductor, commented that stacking can provide successive windows of opportunity, offering levels of integration promised in future generations of memory chips, before a sweet spot of high volume production is reached at the next level of IC integration.

Also noting the rise of stacked CSPs was Steve Greathouse, program manager at Intel, who estimated the total available market for the technology will reach over 8 billion dollars in shipments by 2007. With memory and computing requirements being driven higher, stacking technology provides an optimum solution to augment functionality when space is limited.

At the end of the day, presenters echoed the sentiment that cost and size are of paramount importance, and concurred that elevated dialogue and cooperation is needed throughout the industry to accelerate implementation. Such collaboration between system manufacturers, chipmakers, EMS providers and assemblers &#8212 as well as among competitors &#8212 will be crucial to achieving the goals and promise of increased system-level integration enabled by 3-D packaging technologies.

Copies of the proceedings are available for $50.00 by contacting Daryl Larsen, symposium event manager, at (408) 952-4364, or [email protected].


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