Smaller Die Size Means Capacity Gains

By John R. Lynch

Click here to enlarge image

The continuous push for cost reduction, increased functionality and performance, system compactness, and enhanced quality remain unabated in consumer, communications, defense and medical electronics.

Increased die per wafer as a result of die feature reductions and enhanced utilization of semiconductor substrate material area have resulted in impressive capacity gains as well as cost reductions.

In a relatively short time span, feature sizes on wafers have been reduced in steps from 1.0 µm to 0.13 µm, almost by an order of magnitude. Die sizes have also been reduced in many but not all cases — more function per unit area, in any case — by minimizing the saw kerf area from the former standard of 125 to 150 µm to 50 to 75 µm in roughly the same timeframes as wafer feature sizes (Figure 1). Some newer processes incorporating lasers or a combination of lasers and saws show promise of 25 µm streets. In larger die, such as microprocessors or memories, this is not a big effect, but for other technologies where die are smaller, vertical cavity surface emitting lasers (VCSELs), digital signal processors (DSPs), transistors, diodes, power, etc., this macro change in kerf can account for die per wafer increases of 30 percent or more at the same relative cost. Combine all these size reductions along with the increases in wafer sizes from 150 mm to 300 mm and the number of die as well as the value of the wafer increases tremendously.

Other concurrent system needs require thinner wafers to produce thin die, wafer-level packaging (WLP) designs, chip-scale packages (CSP), stacked wafers and/or die (for thermal efficiency and lowered signal delay), and compact x, y, and z dimensions for handheld devices, and system-on-a-chip (SOC) or system-in-a-package (SIP). All these designs challenge current organizational structure and core competency requirements in a time when those that can compete do so by doing what they do best. It is becoming extremely expensive to maintain such a diverse staff of technologists.

Interconnection evaluations are also progressing to accommodate these small die features: smaller die, thinner wafers/die, lead-free interconnects, stacked die and wafers, all in a journey to nanotechnologies yet to be defined from a packaging perspective.

The obvious conclusion to the interconnection dilemma is to establish better design standards and rely on competent expertise, while moving forward as required. We must depend on standardized manufacturing operations capable of delivering specific interim capabilities on time at cost and with superb quality. This is the definition of the ultimate interconnection subcontractor.

Figure 1. The effect of die saw street (kerf) size reduction on number of die per wafer.
Click here to enlarge image


Is the wafer finishing operation a component of a new business entity? The operation would take those wafer back-end operations, as well as the assembly front-end operations, and combine them, enabling a significant value-added service. This would work in a realm of cleanliness less stringent than a wafer fab (cost savings) and maintain needed expertise in materials processing such as grinding, polishing, thinning, wafer bumping, wafer thru-hole drilling, metallization of wafers and sawing.

Why do this? Wafer back-end has never been a favorite operation for a fab manager, as it is a relatively dirty operation that is usually combined with aggressive etching operations and dangerous chemicals. Also, some metallization requires skills that are significantly different than standard fab operations.

Most fab managers would jump at the chance to outsource grinding and metallization. The same interest level holds true for wafer bumping, and this fact is highlighted by the successful existence of subcontract wafer bumping operations whose specialization in fast bumping turnaround has made them successful. Wafer thinning could be another desirable outsourcing opportunity.

Assembly value-added may ultimately be the test operation as technology migrates to unified and smaller packages, especially in WLPs. Stacked wafers, WLP, CSP, SIP, and system-on-a-package (SOP) will all have their nuances, but core competencies will drive success when incorporated internally or externally. The drivers, cost, peformance, size and quality, will remain.

JOHN R. LYNCH, president, may be contacted at Desert Professional Consulting Inc., 8597 E. Yearling Road, Scottsdale, AZ 85255-1412; phone: (480) 513-2984; e-mail: [email protected].


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.