Sorting Stacked-die
The Challenges of Building SiPs

By Joel McGrath

Many designers have discovered that the benefits of system-on-chips (SoCs) do not always justify the costs. The challenges of combining digital, analog and RF functions, typically optimized for different process technologies, in a single piece of silicon have proved daunting. Moreover, as semiconductor manufacturers have moved down the process path, the mask costs associated with state-of-the-art process technology have skyrocketed. For many design teams today, escalating non-recurring engineering (NRE) costs pose a major risk, especially in an uncertain economy.

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Figure 1. Increasingly popular as a SoC alternative, SiPs offer designers lower cost, a shorter development cycle and the flexibility to change the die in the stack to meet specific application requirements. Photo courtesy of ChipPAC Inc.
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Instead, many designers of PDAs, handheld and wireless devices are turning to stacked-die system-in-package (SiP) alternatives. Designers using this increasingly popular approach to high-density packaging combine multiple stacked die in a chip scale package, often with embedded passive components to create a highly compact solution. By allowing designers to integrate functions by stacking die and connecting them electrically, SiPs give design teams more flexibility than SoCs in a shorter design cycle and at a lower cost. They also allow designers to adapt the individual stacked die to a redesign or die change to meet specific application requirements.

Multiple Challenges

However, designing a SiP, which stacks two, three, four or more die on top of each other, is not a trivial task. Typically, stacked-die SiPs use wirebonding to interconnect to the substrate. In many cases, these configurations require the interleaving of bond fingers in elaborate patterns (Figure 1). Accordingly, a single SiP with multiple die can feature hundreds of wires in a highly complex layout. To increase design flexibility and reduce development time, many designers use multiple-bond patterns to support various die combinations on a single substrate. Often, designers must create complex wirebond patterns — sometimes from die to die — to fit physical constraints. At the same time, they must cope with the electrical constraints of long crossing wires — typically restricted by loop height rules — to ensure signal integrity. Finally, to make matters even more complex, many designs combine flip chip and wirebond technologies in a single stack.

What type of design environment does a designer need to address these problems? Ideally, a designer would use a methodology capable of integrating both electrical analysis and physical design through all development phases to bridge the gap between IC design, package design and package analysis. For physical design, this environment would support input data in multiple formats, provide a comprehensive set of physical layout tools, supply complete documentation and bring all these capabilities together under a constraint manager. Simultaneously, this environment would help designers make crucial electrical tradeoffs to maximize performance, reduce signal corruption, delay and other effects, and minimize the number of design re-spins.

Figure 2. To build stacked-die SiPs, designers must create complex wirebond patterns that meet stringent physical and electrical constraints.
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Flexibility is key in ensuring design success in a stacked-die SiP. First, a design environment for SiPs should offer support for mixed-die interconnect. As designers increasingly integrate digital, analog and RF functions in the same package, they often need to combine flip chip and wirebond technologies. Accordingly, to maximize their flexibility, they need a design methodology that does not restrict their ability to combine different die interconnect technologies. Similarly, the tool environment also should support an unlimited number of die in the same stack.

To maximize designer productivity, the environment should simplify the re-use of design data. If designers can capture substrate stack-up and constraint data in a file, it can be reused for other designs with a similar structure to reduce design time on future projects. In many cases, substrate manufacturers will provide technology files that contain critical design rules to drive a correct-by-design methodology. Multiple technology files then can be used from different suppliers to ensure manufacturability at secondary suppliers.

Multi-step Process

The first question to ask when selecting a development methodology for stacked-die SiPs is: How comprehensive is its packaging support? Ideally, the methodology supports all popular packaging methods as well as flip chip, wirebond and stacked-die attach methods. It also should provide comprehensive design rule checking to support the complex requirements of all the various combinations of laminate, ceramic and deposited substrate technologies. It should accurately verify design accuracy against an extensive set of physical and electrical design rules and automatically check the design against these constraints throughout the design process to ensure the design is meeting manufacturing and electrical specifications. Additionally, the system must provide immediate feedback to the designer through design rule constraint (DRC) markers. Ideally, these capabilities would include some sort of graphic display to illustrate for the designer the complex wirebond pattern, as modifications in the layout are made to accommodate tight spacing or specific manufacturing rules (Figure 2).

The key to simplifying the creation of the complex interconnect patterns inherent in a stacked-die design is an environment that automates the wirebond process. Stacked-die designs typically require the interweaving of bond fingers in complex patterns. To facilitate that process, the design environment should generate multi-tier, multi-die wirebond patterns automatically. It should provide DRCs optimized to address the key metrics in a stacked-die design, including loop height, wire angles and crossing patterns. Moreover, this environment should allow the designer to set specific wire spacing rules for each tier of the design to ensure reliability. This capability allows the designer to enter spacing rules for each wire instead of applying a single set of rules across all wires. The tool should support multi-bond pads and automatically space for escape routing between bond fingers.

Given the unusually large number of nets inherent in a stacked-die package, the design environment also should provide some method for managing and manipulating the nets in a design. Such a tool would allow the designer to cope with different aspect rules in each quadrant of the design.

To maximize design flexibility, the designer must have the ability to generate a pattern of wirebonds, with or without wires on one, multiple or all sides of a die simultaneously. The ability to generate dummy nets also is a highly useful feature — particularly early in the design flow before a netlist has been defined — to allow the designer to run feasibility studies. This permits the designer to place and align wirebond pads based on multiple algorithms and alignment schemes, each with their own constraints. Ideally, the development environment would even allow the designer to set unique loop height, width and wirebond pad settings for each wire. It should allow the designer to set rules that prohibit wires in the same loop height group from crossing, and limit those with different heights to cross only within a user-specified distance from the edge of the die.

Some type of autospacing capability also is crucial in a design environment for stacked-die design because it allows the designer to automatically input routing channels within the bonding pattern to facilitate net routing.

The ability to change or edit the design is key in any project as complex as a stacked-die SiP. Accordingly, the design environment should include a wirebond editing capability or Wizard that simplifies the addition, deletion or movement of wirebond patterns. It should allow the user to make these changes on-the-fly while maintaining existing spacing and other rules.

Electrical Analysis

The development of highly integrated stacked-die SiPs places new demands on electrical modeling and analysis capabilities as well. Ideally, designers need a methodology capable of performing comprehensive package-level interconnect characterization and signal integrity analysis so they can explore design tradeoffs between silicon, package and board.

The ability to explore pre-layout options, design signal and power/ground plane distribution requirements and then implement them in a physical design is essential to achieving shorter design cycles. One way to accomplish this task quickly and efficiently is to be able to sweep aspects of the design, such as I/O driver strength, interconnect lengths and loading conditions, and then simulate them against predefined parameters to define a set of optimized constraints. These constraints then can guide the physical layout of critical paths and the package's power/ground distribution.

To achieve this goal, the designer should be able to define interconnect routing constraints in terms of delay, crosstalk, impedance and inductance. The development environment must highlight constraint violations graphically and allow the user to modify the design, either automatically or manually, to meet tolerances. To maximize designer productivity, it would be advantageous if the designer could receive immediate feedback on constraint violations as the design was modified by performing electrical analysis in real time. If a trace violated a delay propagation constraint, for instance, the tool would allow the designer to gradually add length to the trace and explore different potential solutions until the trace met the specified constraint.

Ideally, this constraint-driven design environment should offer the designer the opportunity to examine the source of potential signal integrity problems in depth. For example, if the design environment highlights a potential violation of a crosstalk constraint assigned to a group of nets, it would be advantageous if the system did more than just identify the violation graphically. Ideally, the designer would like to extract the net in question, run a live simulation on the net, and then review waveform data to identify the extent of the crosstalk at both the driver and receiver end of the net. The designer then could modify the design by spreading the traces out to meet tolerances, run another crosstalk simulation and re-verify that the net met specified constraints.

Differential signaling also is a common feature in stacked-die designs. Through the constraint system, the designer should be able to apply multiple properties to differential nets, including coupling length, phase tolerance, line spacing and coupling parameters. This capability is advantageous when working with a differential bus where the designer can match nets within a specified tolerance. The constraint system then can notify the designer graphically when the differential net is out of tolerance. This capability also allows the designer to modify both traces in a differential pair automatically to resolve DRC violations and ensure signal integrity.

3-D Analysis

To resolve the signal integrity issues associated with wirebond coupling, engineers need a design environment that provides some access to an electromagnetic (EM) field solver to extract the parasitics of the interconnect structures. Few design environments allow the designer to perform 3-D analysis early in the development cycle and integrate it into the design flow. Instead, 3-D analysis typically has been performed by specialists who get involved only after the package design is complete. Problems detected at that late stage in the development process often can be resolved only by workarounds at the board level.

Some design environments available today integrate a 2-D field solver into the design environment and then support 3-D analysis tools from third-party suppliers. With these capabilities, designers can perform an initial top-level extraction using a 2-D field solver and use a third-party 3-D field solver to identify more complex problems such as looking at a via that feeds down through the substrate.

Once the wirebond models are extracted, the design team needs a powerful time domain simulator to simulate performance. Ideally, the designers can extract the models, plug them in, and simulate against them in the same environment to identify problems such as simultaneous switching noise or noise being introduced across the wirebonds.

A new problem confronting package designers building a single stacked-die package that combines various system functions is die-to-die interconnect issues. Most package designers analyze the die-to-pin connection by reviewing the interconnect performance from the silicon pin out to the ball on a BGA, for example. But in a stacked-die configuration, designers also must address the interchip communication from die-to-die.


Designing an interconnect plan for a stack of die is a complex process. The key to building cost-effective stacked-die SiPs and ensuring high reliability will be the availability of comprehensive new design capabilities that optimize and accelerate the package design process by automating wirebonding and integrating physical and electrical constraints into a single, seamless design flow.

JOEL MCGRATH, product marketing manager, IC Packaging Technologies, may be contacted at Cadence Design Systems Inc.; E-mail: [email protected].


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